HYB18T1G400BF_07 Datasheet, PDF (43/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol Note
Self-Refresh Current
I_DD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating,
Data bus inputs are floating.
Operating Bank Interleave Read Current
I_DD7
1. All banks interleaving reads, I_OUT = 0 mA; BL = 4, CL = CL_(IDD), AL = t_RCD(IDD) -1 × t_CK(IDD); t_CK = t_CK(IDD),
t_RC = t_RC(IDD), t_RRD = t_RRD(IDD); tFAW = tFAW(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern:
1)2)3)4)5)
6)
1)2)3)4)5)
6)7)
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks)
DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks)
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) I_DD specifications are tested after the device is properly initialized.
3) I_DD parameter are specified with ODT disabled.
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for I_DD: see Table 47
6) Timing parameter minimum and maximum values for I_DD current measurements are defined in Chapter 7.
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
Description
TABLE 47
Definition for I_DD
defined as V_IN ≤ V_IL(ac).MAX
defined as V_IN ≥ V_IH(ac).MIN
defined as inputs are stable at a HIGH or LOW level
defined as inputs are V_REF = V_DDQ / 2
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
Rev. 1.3, 2007-07
43
03062006-ZNH8-HURV