HYB18T1G400BF_07 Datasheet, PDF (26/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
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Field Bits
Type¹⁾
TABLE 21
EMRS(2) Programming Extended Mode Register Definition (BA[2:0]=010_B)
Description
BA2 16
w
Bank Address
Note: BA2 is not available on 256 Mbit and 512 Mbit components
BA [15:14] w
A
[13:8] w
0_B BA2 Bank Address
Bank Adress
00_B BA MRS
01_B BA EMRS(1)
10_B BA EMRS(2)
11_B BA EMRS(3): Reserved
Address Bus
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
SRF 7
w
000000_B A Address bits
Address Bus, High Temperature Self Refresh Rate for T_CASE > 85°C
0_B A7 disable
1_B A7 enable ²⁾
A
[6:4] w
Address Bus
000_B A Address bits
DCC 3
w
Address Bus, Duty Cycle Correction (DCC)
0_B A3 DCC disabled
1_B A3 DCC enabled
Partial Self Refresh for 4 banks
PASR [2:0] w
Address Bus, Partial Array Self Refresh for 4 Banks³⁾
Note: Only for 256 Mbit and 512 Mbit components
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[1:0]=00, 01)
010_B PASR2 Quarter Array (BA[1:0]=00)
011_B PASR3 Not defined
100_B PASR4 3/4 array (BA[1:0]=01, 10, 11)
101_B PASR5 Half array (BA[1:0]=10, 11)
110_B PASR6 Quarter array (BA[1:0]=11)
111_B PASR7 Not defined
Rev. 1.3, 2007-07
26
03062006-ZNH8-HURV