HYB18T1G400BF_07 Datasheet, PDF (14/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
2.2
Chip Configuration for PG-TFBGA-84
The chip configuration of a DDR2 SDRAM is listed by function in Table 10. The abbreviations used in the Ball#/Buffer Type
columns are explained in Table 11 and Table 12 respectively.
Ball#
Name
Ball
Type
Buffer
Type
Clock Signals ×16 Organization
J8
CK
I
K8
CK
I
K2
CKE
I
Control Signals ×16 Organization
K7
RAS
I
L7
CAS
I
K3
WE
I
L8
CS
I
Address Signals ×16 Organization
L2
BA0
I
L3
BA1
I
L1
BA2
I
M8
A0
I
M3
A1
I
M7
A2
I
N2
A3
I
N8
A4
I
N3
A5
I
N7
A6
I
P2
A7
I
P8
A8
I
P3
A9
I
M2
A10
I
AP
I
P7
A11
I
R2
A12
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Function
TABLE 10
Chip Configuration of DDR SDRAM
Clock Signal CK, CK
Clock Enable
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
Chip Select
Bank Address Bus 2:0
Note: 1 Gbit components and higher
Address Signal 12:0, Address Signal 10/Autoprecharge
Rev. 1.3, 2007-07
14
03062006-ZNH8-HURV