HYB18T1G400BF_07 Datasheet, PDF(24/74 Page) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

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HYB18T1G400BF_07 Datasheet, PDF (24/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

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Internet Data Sheet

HY[B/I]18T1G[40/80/16]0B[C/F](L/V)

1-Gbit Double-Data-Rate-Two SDRAM

Field Bits Type1)

Description

CL

[6:4] w

CAS Latency

Note: All other bit combinations are illegal.

BT

3

w

BL

[2:0] w

011B CL 3

100B CL 4

101B CL 5

110B CL 6

111B CL 7

Burst Type

0B BT Sequential

1B BT Interleaved

Burst Length

Note: All other bit combinations are illegal.

010B BL 4

011B BL 8

1) w = write only register bits

2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and

rounding up to the next integer: WR [cycles] â¥ tWR (ns) / tCK (ns). The mode register must be programmed to fulfill the minimum requirement

for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by tCK.MIN.

%$ %$ %$ $ $ $ $ $ $ $ $ $ $ $ $ $ $

4RII 5' 4 6 '4 6 2&' 3URJUDP

5WW

$/

5WW ',& '/ /

UHJ D GGU

Z Z

Z

Z

Z

Z Z Z

03%7

Field

BA2

BA1

BA0

A13

Qoff

Bits Type1)

16 reg. addr.

15

14

13 w

12 w

Description

TABLE 20

Extended Mode Register Definition (BA[2:0] = 001B)

Bank Address [2]

Note: BA2 not available on 256 Mbit and 512 Mbit components

0B BA2 Bank Address

Bank Address [1]

0B BA1 Bank Address

Bank Address [0]

1B BA0 Bank Address

Address Bus [13]

Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration

0B A13 Address bit 13

Output Disable

0B QOff Output buffers enabled

1B QOff Output buffers disabled

Rev. 1.3, 2007-07

24

03062006-ZNH8-HURV

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