HYB18T1G400BF_07 Datasheet, PDF (52/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Parameter
Symbol
DDR2–667
Unit
Note^{1)2)3)4)5)6)7)}
Min.
Max.
Control & address input pulse width for each input t_IPW
Address and control input setup time
t_IS.BASE
DQ low impedance time from CK/CK
t_LZ.DQ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
MRS command to ODT update delay
t_MOD
Mode register set command cycle time
t_MRD
OCD drive mode output delay
t_OIT
DQ/DQS output hold time from DQS
t_QH
DQ hold skew factor
t_QHS
Average periodic refresh Interval
t_REFI
0.6
200
2 x t_AC.MIN
t_AC.MIN
0
2
0
t_HP – t_QHS
—
—
—
—
—
t_AC.MAX
t_AC.MAX
12
—
12
—
340
7.8
3.9
t_CK.AVG
ps
ps
ps
ns
nCK
ns
ps
ps
µs
µs
23)24)
8)21)
8)21)
34)
34)
25)
26)
27)28)
28)29)
Auto-Refresh to Active/Auto-Refresh command t_RFC
period
127.5
—
ns
30)
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active to active command period for 1KB page
size products
t_RP
t_RPRE
t_RPST
t_RRD
t_RP + 1 × t_CK —
0.9
1.1
0.4
0.6
7.5
—
ns
t_CK.AVG
t_CK.AVG
ns
31)32)
31)33)
34)
Active to active command period for 2KB page t_RRD
10
—
size products
ns
34)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
t_RTP
t_WPRE
t_WPST
t_WR
t_WTR
t_XARD
t_XARDS
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
7 – AL
—
ns
t_CK.AVG
t_CK.AVG
ns
ns
nCK
nCK
34)
34)
34)35)
Exit precharge power-down to any valid
t_XP
2
command (other than NOP or Deselect)
—
nCK
Exit self-refresh to a non-read command
Exit self-refresh to read command
Write command to DQS associated clock edges
t_XSNR
t_XSRD
WL
t_RFC +10
—
200
—
RL–1
ns
34)
nCK
nCK
1) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V.
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. The input reference level for signals other than CK/CK, DQS/DQS,
RDQS / RDQS is defined.
5) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
6) The output timing reference voltage level is V_TT.
Rev. 1.3, 2007-07
52
03062006-ZNH8-HURV