HYB18T1G400BF_07 Datasheet, PDF (58/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
11) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t_CL and t_CH).
12) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
14) 0 °C≤ T_CASE ≤ 85 °C
15) 85 °C < T_CASE ≤ 95 °C
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The t_RRD timing parameter depends on the page size of the DRAM organization. See Table 5 “Ordering Information for Lead-Free
Products (RoHS Compliant)” on Page 5.
18) The maximum limit for the t_WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
19) Minimum t_WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing t_XARDS has to be satisfied.
21) WR must be programmed to fulfill the minimum requirement for the t_WR timing parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded
up to the next integer value. t_DAL = WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
Parameter
TABLE 56
DRAM Component Timing Parameter by Speed Grade - DDR2-400
Symbol
DDR2–400
Min.
Max.
Unit
Note^1)2)3)4)5)
6)
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge t_DAL
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_DELAY
DQ and DM input hold time (differential data t_DH(base)
strobe)
DQ and DM input hold time (single ended data t_DH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
Write command to 1st DQS latching transition t_DQSS
DQ and DM input setup time (differential data t_DS(base)
strobe)
–600
2
0.45
3
0.45
WR + t_RP
t_IS + t_CK + t_IH
275
–25
0.35
–500
0.35
—
– 0.25
150
+600
—
0.55
—
0.55
—
––
––
—
—
+500
—
350
+ 0.25
—
ps
t_CK
t_CK
t_CK
t_CK
t_CK
7)20)
ns
8)
ps
9)
ps
10)
t_CK
ps
t_CK
ps
10)
t_CK
ps
10)
Rev. 1.3, 2007-07
58
03062006-ZNH8-HURV