HYB18T1G400BF_07 Datasheet, PDF (37/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
TABLE 39
OCD Default Characteristics
Symbol
Description
Min.
Nominal Max.
Unit
Note
—
Output Impedance
—
Ω
1)2)
—
Pull-up / Pull down mismatch
0
—
4
Ω
1)2)3)
—
Output Impedance step size
for OCD calibration
0
—
1.5
Ω
4)
S_OUT
Output Slew Rate
1.5
—
5.0
V / ns
1)5)6)7)
1) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: V_DDQ = 1.7 V, V_OUT = 1420 mV; (V_OUT–V_DDQ) / I_OH must be less than
23.4 Ohms for values of V_OUT between V_DDQ and V_DDQ – 280 mV. Impedance measurement condition for output sink dc current:
V_DDQ = 1.7 V; V_OUT = –280 mV; V_OUT / I_OL must be less than 23.4 Ohms for values of V_OUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 Ohms at nominal conditions across all process parameters and represents only
the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18 ± 0.75 Ohms under nominal
conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in t_DQSQ and t_QHS
specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Rev. 1.3, 2007-07
37
03062006-ZNH8-HURV