HYB18T1G400BF_07 Datasheet, PDF (27/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Field Bits
Type¹⁾
Description
Partial Self Refresh for 8 banks
PASR [2:0] w
Address Bus, Partial Array Self Refresh for 8 Banks³⁾
Note: Only for 1G and 2G components
000_B PASR0 Full Array
001_B PASR1 Half Array (BA[2:0]=000, 001, 010 & 011)
010_B PASR2 Quarter Array (BA[2:0]=000, 001)
011_B PASR3 1/8 array (BA[2:0] = 000)
100_B PASR4 3/4 array (BA[2:0]= 010, 011, 100, 101, 110 & 111)
101_B PASR5 Half array (BA[2:0]=100, 101, 110 & 111)
110_B PASR6 Quarter array (BA[2:0]= 110 & 111)
111_B PASR7 1/8 array(BA[2:0]=111)
1) w = write only
2) When DRAM is operated at 85°C ≤ T_Case ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1" before the self
refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost if self refresh
is entered. Data integrity will be maintained if t_REF conditions are met and no Self Refresh command is issued
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Field
BA2
Bits Type¹⁾
16 reg.addr
BA1
15
BA0
14
A
[13:0] w
1) w = write only
TABLE 22
EMR(3) Programming Extended Mode Register Definition(BA[2:0]=011_B)
Description
Bank Address[2]
Note: BA2 is not available on 256 Mbit and 512 Mbit components
0_B BA2 Bank Address
Bank Adress[1]
1_B BA1 Bank Address
Bank Adress[0]
1_B BA0 Bank Address
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
00000000000000_BA[13:0] Address bits
Rev. 1.3, 2007-07
27
03062006-ZNH8-HURV