HYB18T1G400BF_07 Datasheet, PDF (11/74 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HY[B/I]18T1G[40/80/16]0B[C/F](L/V)
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
J1
V_DDL
PWR
J7
V_SSDL
PWR
Not Connected ×4 Organizations
A1, A2, A8, A9, NC
NC
E2, F9, H1,F1,
R7, H9, W1,
W2, W8, W9,
R3
Not Connected ×8 Organization
A1, A2, A8, A9, NC
NC
R7, W1, W2,
W8, W9, R3
Other Balls ×4×8 Organizations
K9
ODT
I
Buffer
Type
—
—
—
—
SSTL
Function
Power Supply
Power Supply
Not Connected
Not Connected
On-Die Termination Control
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 8
Abbreviations for Ball Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
TABLE 9
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.3, 2007-07
11
03062006-ZNH8-HURV