PNX1300 Datasheet, PDF (57/548 Pages) NXP Semiconductors – Media Processors

DSPCPU Architecture
Chapter 3
by Gert Slavenburg, Marcel Janssens
3.1 BASIC ARCHITECTURE CONCEPTS
In the document the generic PNX1300 product name
refers to PNX1300 Series, or the PNX1300/01/02/11
products.
This section documents the system programmer or
‘bare-machine’ view of the PNX1300 CPU (or DSPCPU).
3.1.1 Register Model
Figure 3-1 shows the DSPCPU’s 128 general purpose
registers, r0...r127. In addition to the hardware program
counter, PC, there are 4 user-accessible special purpose
registers, PCSW, DPC (destination program counter),
SPC (source program counter), and CCCOUNT.
Table 3-1 lists the registers and their purposes.
Register r0 always contains the integer value '0', corre-
sponding to the boolean value 'FALSE' or the single-pre-
cision floating point value +0.0. Register r1 always con-
tains the integer value '1' ('TRUE'). The programmer is
NOT allowed to write to r0 or r1.
Note: Writing to r0 or r1 may cause reads from r0 or
r1 scheduled in adjacent clock cycles to return unpre-
dictable values. The standard assembler prevents/
forbids the use of r0 or r1 as a destination register.
Registers r2 through r127 are true general purpose reg-
isters; the hardware does not imply their use in any way,
though compiler or programmer conventions may assign
particular roles to particular registers. The DPC and SPC
relate to interrupt and exception handling and are treated
in Section 3.1.4, “SPC and DPC—Source and Destina-
tion Program Counter.” The PCSW (Program Control
and Status Word) register is treated in Section 3.1.3,
“PCSW Overview.” CCCOUNT, the 64-bit clock cycle
counter is treated in Section 3.1.5, “CCCOUNT—Clock
Cycle Counter.”
Table 3-1. DSPCPU registers
Register Size
Details
r0
32 bits Always reads as 0x0; must not be used
as destination of operations
r1
32 bits Always reads as 0x1; must not be used
as destination of operations
r2–r127 32 bits 126 general-purpose registers
PC
32 bits Program counter
PCSW 32 bits Program control & status word
DPC
32 bits Destination program counter; latches
target of taken branch that is interrupted
SPC
32 bits Source program counter; latches target
of taken branch that is not interrupted
CCCOUNT 64 bits Counts clock cycles since reset
128 General-Purpose Registers
• r0 & r1 fixed
• r2–r127 variable
System Status & Control Registers
63
55
47
39
Figure 3-1. PNX1300 registers.
31
23
15
7
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 r1
r2
r3
•
•
•
•
•
•
r126
r127
31
23
15
7
0
PC
PCSW
DPC
SPC
CCCOUNT
PRELIMINARY SPECIFICATION
3-1