PNX1300 Datasheet, PDF (512/548 Pages) NXP Semiconductors – Media Processors

PNX1300/01/02/11 Data Book
Philips Semiconductors
MMIO Register Name
INTVEC20
INTVEC21
INTVEC22
INTVEC23
INTVEC24
INTVEC25
INTVEC26
INTVEC27
INTVEC28
INTVEC29
INTVEC30
INTVEC31
TIMER1_TMODULUS
TIMER1_TVALUE
TIMER1_TCTL
TIMER2_TMODULUS
TIMER2_TVALUE
TIMER2_TCTL
TIMER3_TMODULUS
TIMER3_TVALUE
TIMER3_TCTL
SYSTIMER_TMODULUS
SYSTIMER_TVALUE
SYSTIMER_TCTL
BICTL
BINSTLOW
BINSTHIGH
BDCTL
BDATAALOW
BDATAAHIGH
BDATAVAL
BDATAMASK
DRAM_CACHEABLE_LIMIT
MEM_EVENTS
DC_LOCK_CTL
DC_LOCK_ADDR
DC_LOCK_SIZE
DC_PARAMS
IC_PARAMS
MM_CONFIG
ARB_BW_CTL
ARB_RAISE
POWER_DOWN
IC_LOCK_CTL
IC_LOCK_ADDR
Offset
(in hex)
10 08d0
10 08d4
10 08d8
10 08dc
10 08e0
10 08e4
10 08e8
10 08ec
10 08f0
10 08f4
10 08f8
10 08fc
10 0c00
10 0c04
10 0c08
10 0c20
10 0c24
10 0c28
10 0c40
10 0c44
10 0c48
10 0c60
10 0c64
10 0c68
10 1000
10 1004
10 1008
10 1020
10 1030
10 1034
10 1038
10 103c
10 0008
10 000c
10 0010
10 0014
10 0018
10 001c
10 0020
10 0100
10 0104
10 010C
10 0108
10 0210
10 0214
Accessibility
DSPCPU
External
PCI
Initiators
Description
R/W
R/W Interrupt vector (handler start address) for source 20
R/W
R/W Interrupt vector (handler start address) for source 21
R/W
R/W Interrupt vector (handler start address) for source 22
R/W
R/W Interrupt vector (handler start address) for source 23
R/W
R/W Interrupt vector (handler start address) for source 24
R/W
R/W Interrupt vector (handler start address) for source 25
R/W
R/W Interrupt vector (handler start address) for source 26
R/W
R/W Interrupt vector (handler start address) for source 27
R/W
R/W Interrupt vector (handler start address) for source 28
R/W
R/W Interrupt vector (handler start address) for source 29
R/W
R/W Interrupt vector (handler start address) for source 30
R/W
R/W Interrupt vector (handler start address) for source 31
R/W
R/W Contains: (maximum count value for timer 1) + 1
R/W
R/W Current value of timer 1 counter
R/W
R/W Timer 1 control (prescale value, source select, run bit)
R/W
R/W Contains: (maximum count value for timer 2) + 1
R/W
R/W Current value of timer 2 counter
R/W
R/W Timer 2 control (prescale value, source select, run bit)
R/W
R/W Contains: (maximum count value for timer 3) + 1
R/W
R/W Current value of timer 3 counter
R/W
R/W Timer 3 control (prescale value, source select, run bit)
R/W
R/W Contains: (maximum count value for system timer) + 1
R/W
R/W Current value of system timer/counter
R/W
R/W System timer control (prescale value, source select, run bit)
R/W
R/W Instruction breakpoint control
R/W
R/W Start of address range that causes instruction breakpoints
R/W
R/W End of address range that causes instruction breakpoints
R/W
R/W Data breakpoint control
R/W
R/W Start of address range that causes data breakpoints
R/W
R/W End of address range that causes data breakpoints
R/W
R/W Compare value for data breakpoints
R/W
R/W Compare mask for compare value for data breakpoints
Cache And Memory System
R/W
R/W
R/W
R/W
R/W
R/—
R/—
R/—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/—
R/—
R/—
R/W
R/W
R/W
R/W
R/W
Start of non-cacheable region in DRAM
Selects two cache-related events for counting
Enable bit for data-cache locking, also PCI hole disable
Start of address range that will be locked into the data cache
Size of address range that will be locked into the data cache
Data-cache geometry (blocksize, associativity, # of sets)
Instruction-cache geometry (blocksize, assoc., # of sets)
DRAM settings (rank size, bus width, refresh interval)
Internal bus arbitration control (bandwidth/latency allocation)
Arbiter Priority Raising timer
Write to this register to initiate power down
Enable bit for instruction-cache locking
Start of address range that will be locked into the instruction
cache
B-2
PRELIMINARY SPECIFICATION