PNX1300 Datasheet, PDF (461/548 Pages) NXP Semiconductors – Media Processors

PNX1300/01/02/11 Data Book
st16d
Philips Semiconductors
16-bit store with displacement
pseudo-op for h_st16d
SYNTAX
[ IF rguard ] st16d(d) rsrc1 rsrc2
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 1
else
bs ← 0
mem[rsrc1 + d + (1 ⊕ bs)] ← rsrc2<7:0>
mem[rsrc1 + d + (0 ⊕ bs)] ← rsrc2<15:8>
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
30
2
7 bits
–128..126 by 2
n/a
4, 5
SEE ALSO
st16 h_st16d st8 st8d st32
st32d
DESCRIPTION
The st16d operation is a pseudo operation transformed by the scheduler into an h_st16d with the same
arguments. (Note: pseudo operations cannot be used in assembly files.)
The st16d operation stores the least-significant 16-bit halfword of rsrc2 into the memory locations pointed to by the
address in rsrc1 + d. The d value is an opcode modifier, must be in the range –128 and 126 inclusive, and must be a
multiple of 2. This store operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
If st16d is misaligned (the memory address computed by rsrc1 + d is not a multiple of 2), the result of st16d is
undefined, and the MSE (Misaligned Store Exception) bit in the PCSW register is set to 1. Additionally, if the TRPMSE
(TRaP on Misaligned Store Exception) bit in PCSW is 1, exception processing will be requested on the next
interruptible jump.
The result of an access by st16d to the MMIO address aperture is undefined; access to the MMIO aperture is
defined only for 32-bit loads and stores.
The st16d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the addressed memory locations (and the modification of cache if the locations are cacheable). If the
LSB of rguard is 1, the store takes effect. If the LSB of rguard is 0, st16d has no side effects whatever; in particular, the
LRU and other status bits in the data cache are not affected.
EXAMPLES
Initial Values
r10 = 0xcfe, r80 = 0x44332211
r50 = 0, r20 = 0xd05,
r70 = 0xaabbccdd
r60 = 1, r30 = 0xd06,
r70 = 0xaabbccdd
Operation
st16d(2) r10 r80
IF r50 st16d(–4) r20 r70
IF r60 st16d(–4) r30 r70
Result
[0xd00] ← 0x22, [0xd01] ← 0x11
no change, since guard is false
[0xd02] ← 0xcc, [0xd03] ← 0xdd
A-163
PRELIMINARYSPECIFICATION