PNX1300 Datasheet, PDF (47/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
Pin List
PNX1300 pin
Output
Buffer
30-ohm
rise/fall test point
2” true length
50-ohm
12 pF
Figure 1-1. STRG3, STRG5 test load circuit
PNX1300 pin
Output
Buffer
rise/fall test point
2” true length
50-ohm
30 pF
CLK
V_test
T_su T_h
V_th
V_tl
Input
V_th
V_test
V_tl
inputs
valid
V_test V_max
Figure 1-5. PCI Input Timing Measurement Conditions
pin
Output
Buffer
25 Ω
1/2 in. max
10 pF
Figure 1-2. NORM3 test load circuit
PNX1300 pin
Output
Buffer
rise/fall test point
2” true length
50-ohm
15 pF
Figure 1-6. PCI T_val(max) Rising Edge
pin
Output
Buffer
10 pF
1/2 in. max
Vcc
25 Ω
Figure 1-3. WEAK5 test load circuit
CLK
Output
Delay
Output
Delay
Tri-State
Output
V_test
T_fval
V_th
V_tl
T_rval
V_tfall
V_trise
T_on
T_off
Figure 1-4. PCI Output Timing Measurement Con-
ditions
Figure 1-7. PCI T_val(max) Falling Edge
pin
Output
Buffer
1K Ω
1/2 in. max
10 pF
Vcc
1K Ω
Figure 1-8. PCI T_val(min) and Slew Rate
TCK
TDI, TMS
T_{su_TCK}
valid
T_{h_TCK}
Figure 1-9. JTAG Input Timing
PRELIMINARY SPECIFICATION
1-21