PNX1300 Datasheet, PDF (388/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
PNX1300/01/02/11 DSPCPU Operations
IEEE status flags from convert floating-point to
integer with round toward zero
ifixrzflags
SYNTAX
[ IF rguard ] ifixrzflags rsrc1 → rdest
FUNCTION
if rguard then
rdest ← ieee_flags((long) ((float)rsrc1))
ATTRIBUTES
Function unit
falu
Operation code
129
Number of operands
1
Modifier
No
Modifier range
—
Latency
3
Issue slots
1, 4
SEE ALSO
ifixrz ufixrzflags
ifixieeeflags
ufixieeeflags
DESCRIPTION
The ifixrzflags operation computes the IEEE exceptions that would result from converting the single-precision
IEEE floating-point value in rsrc1 to a signed integer, and an integer bit vector representing the computed exception
flags is written into r dest. The bit vector stored in rdest has the same format as the IEEE exception bits in the PCSW.
The exception flags in PCSW are left unchanged by this operation. Rounding toward zero is performed; the IEEE
rounding mode bits in PCSW are ignored. If rsrc1 is denormalized, zero is substituted before computing the
conversion, and the IFZ bit in the result is set.
The ifixrzflags operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
31
7
6
5
4
3
2
1
0
0
0 OFZ IFZ INV OVF UNF INX DBZ
EXAMPLES
Initial Values
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
Operation
ifixrzflags r30 → r100
ifixrzflags r35 → r102
IF r10 ifixrzflags r40 → r105
IF r20 ifixrzflags r40 → r110
ifixrzflags r45 → r112
ifixrzflags r50 → r115
ifixrzflags r60 → r117
ifixrzflags r70 → r120
ifixrzflags r80 → r122
Result
r100 ← 0
r102 ← 0x02 (INX)
no change, since guard is false
r110 ← 0x10 (INV)
r112 ← 0x10 (INV)
r115 ← 0x02 (INX)
r117 ← 0x20 (IFZ)
r120 ← 0x10 (INV)
r122 ← 0x10 (INV)
PRELIMINARY SPECIFICATION
A-90