PNX1300 Datasheet, PDF (385/548 Pages) NXP Semiconductors – Media Processors

PNX1300/01/02/11 Data Book
ifixieee
Philips Semiconductors
Convert floating-point to integer using PCSW
rounding mode
SYNTAX
[ IF rguard ] ifixieee rsrc1 → rdest
FUNCTION
if rguard then {
rdest ← (long) ((float)rsrc1)
}
ATTRIBUTES
Function unit
falu
Operation code
121
Number of operands
1
Modifier
No
Modifier range
—
Latency
3
Issue slots
1, 4
SEE ALSO
ufixieee ifixrz ufixrz
DESCRIPTION
The ifixieee operation converts the single-precision IEEE floating-point value in rsrc1 to a signed integer and
writes the result into rdest. Rounding is according to the IEEE rounding mode bits in PCSW. If r src1 is denormalized,
zero is substituted before conversion, and the IFZ flag in the PCSW is set. If ifixieee causes an IEEE exception,
such as overflow or underflow, the corresponding exception flags in the PCSW are set. The PCSW exception flags are
sticky: the flags can be set as a side-effect of any floating-point operation but can only be reset by an explicit
writepcsw operation. The update of the PCSW exception flags occurs at the same time as r dest is written. If any
other floating-point compute operations update the PCSW at the same time, the net result in each exception flag is the
logical OR of all simultaneous updates ORed with the existing PCSW value for that exception flag.
The ifixieeeflags operation computes the exception flags that would result from an individual ifixieee.
The ifixieee operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register. If the LSB of r guard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
Initial Values
r30 = 0x40400000 (3.0)
r35 = 0x40247ae1 (2.57)
r10 = 0,
r40 = 0xff4fffff (–3.402823466e+38)
r20 = 1,
r40 = 0xff4fffff (–3.402823466e+38)
r45 = 0x7f800000 (+INF))
r50 = 0xbfc147ae (-1.51)
r60 = 0x00400000 (5.877471754e-39)
r70 = 0xffffffff (QNaN)
r80 = 0xffbfffff (SNaN)
Operation
Result
ifixieee r30 → r100
r100 ← 3
ifixieee r35 → r102
r102 ← 3, INX flag set
IF r10 ifixieee r40 → r105 no change, since guard is false
IF r20 ifixieee r40 → r110 _{r110 ← 0x80000000 (-2}³¹_{), INV flag set}
ifixieee r45 → r112
ifixieee r50 → r115
ifixieee r60 → r117
ifixieee r70 → r120
ifixieee r80 → r122
r112 ← 0x7fffffff (2³¹-1), INV flag set
r115 ← -2, INX flag set
r117 ← 0, IFZ set
r120 ← 0, INV flag set
r122 ← 0, INV flag set
A-87
PRELIMINARYSPECIFICATION