PNX1300 Datasheet, PDF (207/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
System Boot
13.4 DETAILED EEPROM CONTENTS
Table 13-5 shows the serial EEPROM contents needed
for an autonomous boot procedure. For the host-assisted
boot procedure, only the contents up to line nine are
needed.
Note that the 32-bit words in the serial EEPROM are not
stored on 32-bit word-aligned addresses.
Table 13-5. Serial boot EEPROM contents
Line
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
bit 7
#lines
0: 128 lines
1: 256 or more
lines
—
sdram PLL
bypass
boot type
0: host assist.
1: autonomous
Data Byte
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SDRAM size[2:0]
000: 1MB
001: 1MB
010: 2MB
011: 4MB
100: 8MB
101: 16MB
110: 32MB
111: 64MB
BOOT_CLK[1:0]
00: 100 MHz
01: 75 MHz
10: 50 MHz
11: 33 MHz
EEPROM
clock
0: 100 KHz
1: 400 KHz
Subsystem ID, 8 msb
Subsystem ID, 8 lsb
Subsystem Vendor ID, 8 msb
Subsystem Vendor ID, 8 lsb
—
—
—
MM_CONFIG[19:16]
MM_CONFIG[15:8]
MM_CONFIG[7:0]
PLL_RATIOS[7:0]
sdram PLL dis-
able
cpu PLL bypass
cpu PLL disable
sdram ratio
cpu ratio[2:0]
enable inter-
nal PCI_CLK
SDRAM
prefetchable
0:no 1:yes
—
—
byte count [10:8]
byte count [7:0]
MMIO_BASE address [31:24] (must be 0xEF)
MMIO_BASE address [23:16] (must be 0xF0)
MMIO_BASE address [15:8] (must be 0x04)
MMIO_BASE address [15:8] (must be 0x00)
MMIO_BASE value [31:24]
MMIO_BASE value [23:16]
MMIO_BASE value [15:8]
MMIO_BASE value [7:0]
DRAM_BASE address [31:24] (must be byte 3 of MMIO_BASE + 0x100000)
DRAM_BASE address [23:16] (must be byte 2 of MMIO_BASE + 0x100000)
DRAM_BASE address [15:8] (must be byte 1 of MMIO_BASE + 0x100000)
DRAM_BASE address [7:0] (must be byte 0 of MMIO_BASE + 0x100000)
DRAM_BASE value [31:24]
DRAM_BASE value [23:16]
DRAM_BASE value [15:8]
DRAM_BASE value [7:0]
DRAM_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100004)
DRAM_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100004)
DRAM_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100004)
DRAM_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100004)
DRAM_LIMIT value [31:24]
DRAM_LIMIT value [23:16]
DRAM_LIMIT value [15:8]
DRAM_LIMIT value [7:0]
DRAM_CACHEABLE_LIMIT address [31:24] (must be byte 3 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [23:16] (must be byte 2 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [15:8] (must be byte 1 of MMIO_BASE + 0x100008)
DRAM_CACHEABLE_LIMIT address [7:0] (must be byte 0 of MMIO_BASE + 0x100008)
Test Mode
0: normal
1: rapid ATE
PRELIMINARY SPECIFICATION
13-7