PNX1300 Datasheet, PDF (324/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
PNX1300/01/02/11 DSPCPU Operations
Dual clipped add of signed 16-bit halfwords
dspidualadd
SYNTAX
[ IF rguard ] dspidualadd rsrc1 rsrc2 → rdest
FUNCTION
if rguard then {
temp1 ← sign_ext16to32(rsrc1<15:0>) + sign_ext16to32(rsrc2<15:0>)
temp2 ← sign_ext16to32(rsrc1<31:16>) + sign_ext16to32(rsrc2<31:16>)
if temp1 < 0xffff8000 then temp1 ← 0x8000
if temp2 < 0xffff8000 then temp2 ← 0x8000
if temp1 > 0x7fff then temp1 ← 0x7fff
if temp2 > 0x7fff then temp2 ← 0x7fff
rdest<31:16> ← temp2<15:0>
rdest<15:0> ← temp1<15:0>
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dspalu
70
2
No
—
2
1, 3
SEE ALSO
dspidualabs dspidualmul
dspidualsub dspiabs
DESCRIPTION
As shown below, the dspidualadd operation computes two 16-bit clipped, signed sums separately on the two
pairs of high and low 16-bit halfwords of rsrc1 and rsrc2. Both sums are clipped into the range [2¹⁵–1..–2¹⁵] (or
[0x7fff..0x8000]) and written into the corresponding halfwords of rdest. All values are signed 16-bit integers.
31
rsrc1
signed
15
0
signed
31
rsrc2
signed
15
0
signed
+
+
17
0
17
0
Two full-precision
17-bit signed sums
signed
signed
Clip to [2¹⁵–1 .. –2¹⁵]
Clip to [2¹⁵–1 .. –2¹⁵]
31
rdest
signed
15
0
signed
The dspidualadd operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
Initial Values
r30 = 0x12340032, r40 = 0x00010002
r10 = 0, r30 = 0x12340032, r40 = 0x00010002
r20 = 1, r30 = 0x12340032, r40 = 0x00010002
r50 = 0x80000001, r80 = 0xffff7fff
r110 = 0x00017fff, r120 = 0x7fff7fff
Operation
dspidualadd r30 r40 → r60
IF r10 dspidualadd r30 r40 → r70
IF r20 dspidualadd r30 r40 → r100
dspidualadd r50 r80 → r90
dspidualadd r110 r120 → r125
Result
r60 ← 0x12350034
no change, since guard is
false
r100 ← 0x12350034
r90 ← 0x80007fff
r125 ← 0x7fff7fff
PRELIMINARY SPECIFICATION
A-26