PNX1300 Datasheet, PDF (251/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
I2C Interface
ENABLE bit effectively resets the entire I²C interface,
including all status and interrupt flag bits. A transfer
in progress is aborted and the byte currently trans-
ferred is lost.
Note: For writes, Reserved1, 2, 3 and 4 bitfields
MUST always be written with ‘0’s.
16.5 I²C SOFTWARE OPERATION MODE
I²C software operation mode is intended for use by soft-
ware I²C or similar algorithm implementations. In this
case, the SCL and SDA pins are fully controlled and ob-
served by software, and the hardware I²C interface is
disconnected from the SCL and SDA pins. Refer to
Figure 16-3 for a clarification of the principles involved.
Software mode is by default disabled after boot. Soft-
ware mode is enabled by writing a ‘1’ to
IIC_CR.SW_MODE_EN. At that point, the SCL and SDA
pins can be controlled by the IIC_CR SDA_OUT and
SCL_OUT bits. Writing a ‘1’ to either bit causes the cor-
responding pin to become active, i.e. be pulled low. The
SDA and SCL lines are open-collector outputs, and can
hence also be pulled low by external devices. The actual
pin state can be observed by software by examining
IIC_SR SDA_STAT and SCL_STAT bits. A 1 in these
MMIO bits indicates that the corresponding pin is cur-
rently pulled low.
By appropriate software, possibly using a timer interrupt,
full I²C functionality can be implemented using this
mechanism.
16.6 I²C HARDWARE OPERATION MODE
Hardware operation of I²C is the default mode after boot.
The PNX1300 I²C hardware interface operates in one of
two modes:
1. Master-transmitter (to write data to a slave)
2. Master-receiver (to read data from a slave)
As a master, the I²C logic will generate all the serial clock
pulses and the START and STOP bus conditions. The
START and STOP bus conditions are shown in
Figure 16-4. A transfer is ended with a STOP condition
or a repeated START condition. Since a repeated
START condition is also the beginning of the next serial
transfer, the I²C bus will not be released.
Note: The I²C interface on PNX1300 will operate as a
master ONLY!
The number of bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each 8-bit data byte is followed by one acknowl-
edge bit. The transmitter releases the SDA line which will
pull-up to a HIGH level during the acknowledge bit time.
The receiver acknowledges by pulling the data line LOW
sw_mode_en
I2C
hardware
scl_out
DQ
open drain
buf
SCL
scl_stat
tribuf
sw_mode_en
sda_out
DQ
open drain
buf
sda_stat
tribuf
SDA
DATA
HIWAY
Figure 16-3. I²C software mode only logic
PRELIMINARY SPECIFICATION
16-5