PNX1300 Datasheet, PDF (534/548 Pages) NXP Semiconductors – Media Processors

A B CD E F GH I J K L MNO PQR S T U VWX Y Z
igeq A-96
igeqi A-97
igtr A-98
igtri A-99
iimm A-100
iis 8-1
ijmpf A-101
ijmpi A-102
ijmpt A-103
ild16 A-104
ild16d A-105
ild16r A-106
ild16x A-107
ild8 A-108
ild8d A-109
ild8r A-110
ileq A-111
ileqi A-112
iles A-113
ilesi A-114
image
ICP input format 14-3
processing algorithm s14-6
resizing 14-6
scaling 14-6
scaling factor rang e14-3
size range 14-3
Image co-processor
block diagram 14-1
image co-processor 14-1
block diagram 14-2
image formats 14-3
image overlay 14-1, 14-5, 14-9
image overlay formats
of ICP,table 14-5
image processing
bandwidth 14-1
IMASK
picture 3-11
imax A-115
imin A-116
imul A-117
imulm A-118
ineg A-119
ineq A-120
ineqi A-121
initialization
DRAM memory syste m12-6
instruction cache 5-10
initialization,cache 5-8
inonzero A-122
input format
ICP 14-3
input grid
relating to output grid 14-7
instruction breakpoint 3-13
instruction cache 5-8
address mapping 5-8
picture 5-9
coherency 5-11
initialization and boot 5-10
LRU replacement 5-11
performance evaluation support 5-12
instruction cache parameters 5-8
instruction cache set 5-8
instruction cache tag 5-8
instruction cache,summary 5-8
INT_CTL
PCI interface MMIO register 11-15
picture 3-12, 11-10
integer representatio n3-4
interleaving
of SDRAM 12-6
interrupt line
PCI interface register 11-9
interrupt mask 3-10
interrupt mode 3-10
interrupt pin
PCI interface register 11-9
interrupt priority 3-10
interrupt vectors 3-9
interrupts 3-9
definition 3-9
DSPCPU enable bit 3-2
interspersed sampling 6-5
intervals
refresh 12-6
INTVEC[31:0]
picture 3-9
IO_ADR
PCI interface MMIO register 11-13
picture 11-10
IO_CTL
PCI interface MMIO register 11-13
picture 11-10
IO_DATA
PCI interface MMIO register 11-13
picture 11-10
IPENDING
picture 3-11
IS 11172-2 references 15-3
IS 13818-2 references
table 15-3
ISETTING0
picture 3-10
ISETTING1
Index-8
PRELIMINARY SPECIFICATION