PNX1300 Datasheet, PDF (428/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
32-bit load with displacement
PNX1300/01/02/11 DSPCPU Operations
ld32d
SYNTAX
[ IF rguard ] ld32d(d) rsrc1 → rdest
FUNCTION
if rguard then {
if PCSW.bytesex = LITTLE_ENDIAN then
bs ← 3
else
bs ← 0
rdest<7:0> ← mem[rsrc1 + d + (3 ⊕ bs)]
rdest<15:8> ← mem[rsrc1 + d + (2 ⊕ bs)]
rdest<23:16> ← mem[rsrc1 + d + (1 ⊕ bs)]
rdest<31:24> ← mem[rsrc1 + d + (0 ⊕ bs)]
}
ATTRIBUTES
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
dmem
7
1
7 bits
–256..252 by 4
3
4, 5
SEE ALSO
ld32 ld32r ld32x st32
st32d h_st32d
DESCRIPTION
The ld32d operation loads the 32-bit memory value from the address computed by rsrc1 + d and stores the result
in rdest. The d value is an opcode modifier, must be in the range –256 to 252 inclusive, and must be a multiple of 4. If
the memory address computed by rsrc1 + d is not a multiple of 4, the result of ld32d is undefined but no exception
will be raised. This load operation is performed as little-endian or big-endian depending on the current setting of the
bytesex bit in the PCSW.
The ld32d operation can be used to access the MMIO address aperture (the result of MMIO access by 8- or 16-bit
memory operations is undefined). The state of the BSX bit in the PCSW has no effect on MMIO access by ld32d.
The ld32d operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
modification of the destination register and the occurrence of side effects. If the LSB of rguard is 1, rdest is written and
the data cache status bits are updated if the addressed locations are cacheable. if the LSB of rguard is 0, rdest is not
changed and ld32d has no side effects whatever.
EXAMPLES
Initial Values
Operation
Result
r10 = 0xcfc,
[0xd00] = 0x84, [0xd01] = 0x33,
[0xd02] = 0x22, [0xd03] = 0x11
r30 = 0, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r40 = 1, r20 = 0xd0c,
[0xd04] = 0x48, [0xd05] = 0x66,
[0xd06] = 0x55, [0xd07] = 0x44
r50 = 0xd01
ld32d(4) r10 → r60
r60 ← 0x84332211
IF r30 ld32d(-8) r20 → r70 no change, since guard is false
IF r40 ld32d(-8) r20 → r80 r80 ← 0x48665544
ld32d(-8) r50 → r90
r90 undefined, since 0xd01 +(–8) is not a
multiple of 4
PRELIMINARY SPECIFICATION
A-130