PNX1300 Datasheet, PDF (521/548 Pages) NXP Semiconductors – Media Processors

Philips Semiconductors
Endian-ness
Big Endian Mode
P_n+1
A+3 A+2
P_n
A+1
A+0
Little Endian Mode
P_n+1
A+3 A+2
P_n
A+1
A+0
Pixel half-word data
in memory or PCI
V0α1 Y1
V1α3 Y3
31
U0α0
U1α2
Y0
Y2
0
Y1
Y3
31
V0α1
V1α3
Y0 _U0α0
Y2 _U1α2
0
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
Figure C-6. Packed YUV 4:2:2+α data format for the ICP or VO in Little and Big Endian modes
Big Endian Mode
P_n+1
A+3 A+2
P_n
A+1
A+0
Little Endian Mode
P_n+1
A+3 A+2
P_n
A+1
A+0
Pixel half-word data
V0
Y1
U0
in memory or PCI
V1
Y3
U1
31
Y0
Y1
V0
Y2
Y3
V1
0
31
Y0
U0
Y2
U1
0
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
Figure C-7. Packed YUV 4:2:2 data format for ICP in Little and Big Endian modes
Big Endian Mode
P_n+1
A+3 A+2
P_n
A+1
A+0
Little Endian Mode
P_n+1
P_n
A+3
A+2
A+1
A+0
Pixel half-word data
in memory or PCI
G1B1
G3B3
31
R1G’1 G0B0
R3G’3 G2B2
R0G’0
R2G’2
0
R1G’1
R3G’3
31
G1B1 R0G’0
G3B3 R2G’2
G0B0
G2B2
0
Note: A+0 corresponds to byte-0 lane of SDRAM/Hwy/PCI
and A+3 corresponds to byte-3 lane of SDRAM/Hwy/PCI
Figure C-8. RBG-16 data format for ICP in Little and Big Endian modes
PRELIMINARY SPECIFICATION
C-5