SAA2501 Datasheet, PDF (40/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 40 Testing L3RDY by polling L3DATA; note 1
L3DATA
01100011
polled
TRANSFER
SOURCE
host
SAA2501
L3MODE
0
1
EXPLANATION
write ‘read status’ operational address
test L3DATA; repeat this step until L3DATA = 1
Note
1. No status byte transfers are needed; the load of the host (microcontroller) can thus be reduced.
8.2.2
OPTIONS TO INCREASE THE TIMING ACCURACY OF
THE APU COEFFICIENT WRITING
The SAA2501 offers three enhancements to increase the
timing accuracy with which APU coefficients can be
updated by the application:
1. Status polling is not required when APU coefficients
are written. L3 status flag L3RDY, when read anyhow,
will always be HIGH, indicating that the next APU
coefficient transfer may be done. The transfer speed is
only limited by the maximum allowed frequency of
L3CLK. As a result, also no ‘write item data’
operational address is needed any more before writing
each APU coefficient index.
2. Normally, no more bytes may be written to a writeable
data item than the length of that specific item. An
exception is formed by the APU coefficients. They may
be written continuously with a coefficient wrap. After
the writing of all 4 coefficients, the writing can be
continued at the first APU coefficient without having to
write a new control byte.
3. The data item transfer protocol, described in
Section 7.20.6, although transparent, allows only for
the reading or writing of data items from their first data
byte onwards. This approach can lead to situations
where e.g. 54 Ancillary Data item bytes must all be
read (which takes at least 54 × 200 µs = 10.8 ms, due
to the interface speed limitations: see Section 7.20.6)
before the next data item can be transferred. The
SAA2501 enables the writing of APU coefficients
without having to wait for the current item transfer to
finish. In order to do so, a running transfer can be
interrupted by an APU coefficient write transfer, and
then be resumed with the ‘continue current transfer’
control byte.
An item transfer may be interrupted at any time to write
APU coefficients. After the ‘continue previous transfer’
control byte, a operational address must always follow,
indicating the type of L3 transfer that will follow. An
APU coefficient write transfer itself cannot be
interrupted.
January 1995
40