SAA2501 Datasheet, PDF (28/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
7.20.7 SAA2501 SETTINGS ITEM
The SAA2501 is configured with the SAA2501 settings. The initial value of the SAA2501 settings after reset is all zeros.
Table 21 SAA2501 settings item; 1 byte (read/write)
7
MSEL1⁽¹⁾
6
MSEL0⁽¹⁾
5
CRCACT⁽²⁾
4
MCKDIS⁽³⁾
3
FCKENA⁽⁴⁾
2
SELCH2⁽⁵⁾
1
RND1⁽⁶⁾
0
RND0⁽⁶⁾
Notes
1. MSEL1 and MSEL0; these bits select the used input interface, the input data format and the input synchronization
type (see Table 22).
2. CRCACT; automatic/forced CRC activity:
a) CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine the presence of
the CRC.
b) CRCACT = 1; the SAA2501 assumes the CRC always to be present. The protection bit in the used ISO/MPEG
frame header is forced to 0.
3. MCKDIS; buffered master clock MCLK disabling:
a) MCKDIS = 0; enable MCLK.
b) MCKDIS = 1; disable (3-state) MCLK.
4. FCKENA; buffered 256f_s or 384f_s output signal FSCLK enabling:
a) FCKENA = 0; disable (3-sate) FSCLK.
b) FCKENA = 1; enable FSCLK.
5. SELCH2; with dual channel mode input data (with other modes of input data ‘don’t care’:
a) SELCH2 = 0; select channel I.
b) SELCH2 = 1; select channel II.
6. RND1 and RND0; these bits select the rounding of the baseband audio output samples (see Table 23).
Table 22 MSEL1 and MSEL0
MSEL1
0
0
1
1
MSEL0
0
1
0
1
USED INPUT INTERFACE
master
EU147
slave
slave
INPUT SYNCHRONIZATION
to ISO/MPEG synchronization pattern
to synchronization signal CDSSY
to ISO/MPEG synchronization pattern
to synchronization signal CDSSY
Table 23 RND1 and RND0
RND1
0
0
1
1
RND0
0
1
0
1
16 bits
18 bits
20 bits
22 bits
OUTPUT SAMPLE ROUNDING LENGTH
January 1995
28