SAA2501 Datasheet, PDF (35/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
8.1.1.2 Special function operational address
Preliminary specification
SAA2501
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L3CLK
L3DATA
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MGB504
Fig.17 Data transfer mode.
Operational address 000000 (bit 2 to bit 7) is the special
function address, and is used for the L3 device reset, as
well as for the declaration and invalidation of the extended
addressing. Both will be explained in Sections 8.1.2 and
8.1.3.
8.1.1.3 Data mode
In the data mode (see Fig.17) the microcontroller sends or
receives information to or from the selected device. During
data transfer the L3MODE line is HIGH. The L3CLK line is
lowered 8 times during which the L3DATA line carries
8 bits. The information is presented LSB first and remains
stable during the LOW phase of the L3CLK signal.
The preferred basic data transfer unit is an 8 bit byte.
Some implementations that are modifications of earlier
circuits with 16 bit registers may use a basic unit of 16 bits,
transferred as 2 bytes, with the most significant byte
presented first. No other basic data transfer unit is allowed.
8.1.1.4 Halt mode
In between units the L3MODE line will be driven LOW by
the microcontroller to indicate the completion of a basic
unit transfer. This is called ‘halt mode’ (HM). During halt
mode the L3CLK line remains HIGH (to distinguish it from
an addressing mode). The halt mode allows an
implementation of an interface module without a bit
counter. However, an implementation using a bit counter
in the interface module may allow for the L3MODE line to
be kept HIGH in between units (not using the halt mode).
This implementation must also operate correctly if the halt
mode is used. The documentation of the device will have
to indicate clearly whether or not the ‘halt mode’ is
necessary for correct operation of the interface.
8.1.2 DEVICE INTERFACE RESET
If the microcontroller sends an operational address
‘000000’ with DOM1 and DOM0 also equal to ‘0’ this
indicates that none of the L3 interface devices is allowed
to communicate with the microcontroller during the
following data mode. This enables a different application of
the L3CLK and L3DATA lines as the L3 devices will not
interfere with any communication on these lines as long as
L3MODE remains HIGH (e.g. the L3CLK and L3DATA
lines are normally connected to USART circuits in the
microcontrollers which allow for convenient
communication between microcontrollers).
Any addressing mode with a valid L3 operational address
will re-enable the communication with the corresponding
device.
Devices with a fixed operational address (‘Primary L3
devices’) will react with a device reset condition regardless
of the state of DOM1 and DOM0.
Devices with a programmable operational address
(‘Secondary L3 devices’) can only be put in the interface
reset condition if the DOM1 and DOM0 bits are ‘0’. Other
combinations of DOM1 and DOM0 initiate data transfers
for ‘extended addressing’.
8.1.3 EXTENDED ADDRESSING
L3 Devices with a programmable address can be informed
of their operational address using a special data transfer.
January 1995
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