SAA2501 Datasheet, PDF (17/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
handbook, full pagewidth
CDS
CDSCL
CDSWA
CDSSY
valid data
frame start
invalid data
MGB497
CDSSY indicates frame start at next valid data.
Fig.9 Input data serial transfer format (slave input).
Whether frame sync signal CDSSY is present or not must
be selected with L3 settings flags MSEL1 and MSEL0
(see Section 7.20.7). With respect to the presence of
CDSSY, two situations can be distinguished:
1. For EU147 coded input data CDSSY is mandatory.
2. For ISO/MPEG input data if CDSSY is supplied,
CDSWA may change each CDSCL period.
3. If CDSSY is not supplied, CDSCL must have a
frequency higher than the bit rate (i.e. CDSWA
cannot be continuously HIGH), and CDSWA HIGH
periods may have only lengths of a multiple of
8 CDSCL periods: data is input in byte bursts.
Furthermore, these bursts must be byte aligned with
the frame bounds: frames are only allowed to start at
the 1^st, 9^th, 17^th etc. bit in a valid data burst. For
applications where data is input in bursts of exactly
one frame, and where CDSCL has a higher frequency
than the bit rate, CDSWA and CDSSY may be
interconnected.
7.17.3 SLAVE INPUT TRANSFER SPEED OF FIRST FRAME
Both the average and the instantaneous speed at which
data is transferred to the slave input interface are limited.
The data transferring of the first ISO/MPEG or EU147
frame after starting to decode is shown in Fig.10.
It shows the transferring of n-frame bits in one frame
between time 0 and t, where t corresponds to 384 sample
periods (ISO/MPEG layer I input data) or 1152 sample
periods (ISO/MPEG layer II input data). Buffer margin B
equals 16 bytes (128 bits). In Fig.10 an effective
transferring characteristic is drawn, representing any of
the possible ISO/MPEG bit rates. However, input data may
be transferred at a higher-than-effective speed (in other
words: CDSCL may have a higher frequency than the
effective bit rate) in periods during which CDSWA is HIGH,
interleaved with invalid data periods where CDSWA is
LOW. In the example of Fig.9 this is used to transfer the
data of the frame in two bursts, as shown by the actual
transferring characteristic. The actual transferring
characteristic has a slope equal to the CDSCL frequency
while CDSWA is HIGH, and is horizontal during the
periods in which CDSWA is LOW (no bits are being
transferred).
January 1995
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