SAA2501 Datasheet, PDF (31/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 28 ASSD item; 2 bytes (read-only)
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
ASSD
bytes 1 and 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
The ASSD item and the (extended) Program Associated Data [(X)PAD] item (see Section 7.20.11) may be read together
as a single item.
7.20.11 ANCILLARY DATA/XPAD ITEM
The last 54 bytes of each ISO/MPEG frame, which may carry Ancillary Data (AD), are buffered by the SAA2501 to be
read by the host. The subsequent Ancillary Data bytes are read in reversed order with respect to their order in the input
data bitstream. The first item data byte is the last frame byte in the input bitstream. The Ancillary Data item is refilled at
every frame. The host must either know or determine itself how many of the Ancillary Data bytes are valid per frame. The
Ancillary Data item only has significance if status flag INSYNC is set.
Table 29 Ancillary Data item; 54 bytes (read-only)
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
AD byte 1 to
AD byte 54
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Likewise, when EU147 input data is being decoded, the PAD and XPAD bytes contained in each frame may be read,
with the 2 PAD bytes first, followed by a maximum of 52 XPAD bytes. The subsequent PAD and XPAD bytes are read
in reversed order with respect to their order in the input data bitstream. The first item data byte is the last PAD byte in
the input bitstream. The host must determine itself how many of the XPAD bytes are valid per frame by interpretation on
the PAD. The (X)PAD item only contains significant data if status flag INSYNC is set.
Table 30 (X)PAD item; 54 bytes (read-only)
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
PAD byte 1
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PAD byte 2
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
XPAD
bytes 1 to 52
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
7.20.12 APU COEFFICIENTS ITEM
The APU coefficients are set by writing their 8 bit indices to the 4-byte APU coefficient item. Only the 7 LSBs are valid.
The MSB must be zero. At a device reset, indices LL and RR are set to 00000000 (‘no attenuation’) and indices LR and
RL to 01111111 (infinite attenuation; no crosstalk).
January 1995
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