SAA2501 Datasheet, PDF (32/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 31 APU coefficients item; 4 bytes (write-only); see note 1
SUBSEQUENT
BYTES
7
6
5
4
3
2
1
0
APU coefficient LL
0
LL.6
LL.5
LL.4
LL.3
LL.2
LL.1
LL.0
APU coefficient LR
0
LR.6
LR.5
LR.4
LR.3
LR.2
LR.1
LR.0
APU coefficient RL
0
RL.6
RL.5
RL.4
RL.3
RL.2
RL.1
RL.0
APU coefficient RR
0
RR.6
RR.5
RR.4
RR.3
RR.2
RR.1
RR.0
Note
1. Multiple options are supplied by the SAA2501 to increase the timing accuracy of the APU coefficient writing
(see Section 8.2).
7.20.13 SPEED LIMITATIONS OF THE L3 INTERFACE
When reading the status of, or writing control bytes to the
SAA2501, no status polling is necessary, so the speed of
these transfers is only limited by the maximum frequency
of signal L3CLK and the timing constraints of the L3
protocol.
When reading or writing data item bytes, status polling is
necessary. In addition to the speed limitation this poses,
the application must take precautions that individual data
item bytes are transferred at an interval of at least 200 µs.
Neither the status polling nor a minimum interval between
transfers is required when transferring the APU coefficient
item.
7.20.14 DEFAULT ITEM DATA VALUES AFTER RESET
At a device reset, the L3 interface initialization procedure
must be followed. All writeable data items are pre-loaded
with a defined default value after the device reset signal
has been de-activated. These default values are
summarized in Table 32.
Table 32 SAA2501 settings item; default value after device reset (notes 1 to 6)
SUBSEQUENT
BYTES
SAA2501 settings
Value
7
MSEL1
0
6
5
4
3
2
MSEL0 CRCACT MCKDIS FCKENA SELCH2
0
0
0
0
0
1
RND1
0
0
RND0
0
Notes
1. MSEL1 = 0 and MSEL0 = 0; the master input is selected. The SAA2501 synchronizes to the ISO/MPEG
synchronization pattern.
2. CRCACT = 0; the SAA2501 uses the protection bit in the ISO/MPEG frame header to determine if the CRC is active.
3. MCKDIS = 0; the buffered master clock output MCLK is enabled.
4. FCKENA = 0; the buffered 256f_s or 384f_s clock output is disabled.
5. SELCH2 = 0; when decoding input data with dual channel mode, channel I is output on both baseband audio output
channels.
6. RND1 = 0 and RND0 = 0; the baseband audio output signals are rounded to 16 bit.
January 1995
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