SAA2501 Datasheet, PDF (37/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
8.1.4 EXAMPLE OF A DATA TRANSFER
handbook, full pagewidth
L3MODE
L3CLK ⁽¹⁾
L3DATA(2)
address
(1) L3CLK is triggered by L3MODE.
(2) For more details (see Fig.20).
data
byte 1
data
byte 2
data
byte 3
data
byte 4
Fig.18 Example of transfer of 4 bytes.
address
MGB506
A data transfer starts when the microcontroller sends an
address on the bus. All ICs will evaluate this address, but
only the IC addressed will be an active partner for the
microcontroller in the following data transfer mode.
During the data transfer mode bytes will be sent from or to
the microcontroller. In this example the L3MODE line is
made LOW (‘halt mode’) in between byte transfers. This is
the default operation, although some ICs may allow the
L3MODE line to be kept HIGH. This exception must be
specified clearly in the IC documentation, and such ICs
must be able to communicate with microcontrollers that
make L3MODE LOW in between transfers. It is suggested
that new designs only use bytes as basic data transfer
units. After the data transfer the microcontroller does not
need to send a new address until a new data transfer is
necessary. Alternatively it may also send the ‘special
address’ 000000 to indicate the end of the data transfer
operation.
8.1.5 TIMING REQUIREMENTS
These are requirements for the slave devices designed
according to the 'L3' interface definitions.
8.1.5.1 Addressing mode
handbook, full pagewidth
t _d1
th2
L3MODE
t _cL
t _cH
L3CLK
L3DATA
t _h1
t _su
Fig.19 Addressing mode timing.
MGB507
January 1995
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