SAA2501 Datasheet, PDF (10/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 2 Target applications
ATTRIBUTE CONDITIONS
INPUT INTERFACE
FSCLKM
MCLKIN
X22IN
FSCLKIN
FSCLK
CONDITIONS
MCLK24 = 1
MCLK24 = 0
FSCLK384 = 1
FSCLK384 = 0
FCKENA = 1 (L3)
SLAVE INPUT
S⁽¹⁾
X
24.576 MHz
12.288 MHz
note 3
384f_s
256f_s
copy of FSCLKIN
APPLICATION
MASTER INPUT
M0⁽²⁾
M1
0
24.576 MHz
illegal
22.579 MHz
illegal
note 3
256f_s
1
24.576 MHz
12.288 MHz
note 3
384f_s
256f_s
copy of FSCLKIN
Notes
1. FSCLKIN must be locked to input data clock CDSCL; see Section 7.17.2.
2. FSCLKIN is not used, but FSCLK384 must be LOW.
3. Must be electrically defined; e.g. LOW.
Sections 7.5 and 7.6 explain which clock sources are
activated by the SAA2501 depending on the selected input
interface. This automatic clock source selection makes it
easy to apply the SAA2501 in systems with two
ISO/MPEG coded data sources (one connected to the
master input, an one to the slave input), even if these data
sources use different clocks.
7.8 Buffered clock outputs
The SAA2501 provides a signal MCLK which is a buffered
version of MCLKIN. MCLK can be set to 3-state by setting
the L3 control interface flag MCKDIS to 1 in applications
where MCLK is not needed.
Signal FSCLK is copied from the FSCLKIN input for
application types S and M1 or generated with a frequency
of 256f_s by the SAA2501 for application type M0. After a
device reset, FSCLK must be enabled explicitly by setting
L3 flag FCKENA, or can alternatively be left 3-stated in
applications where it is not needed.
After a device reset, MCLK is enabled; FSCLK is disabled
(i.e. both MCKDIS and FCKENA are set to logic 0).
7.9 Functionality issues
The SAA2501 fully complies with ISO/MPEG layer I and II
and EU147 with the slave input. With the master input, the
SAA2501 complies with ISO/MPEG layer I and II,
excluding the free format bit rate. Several aspects of the
decoding process, as well as the audio post-processing
features, offered by the SAA2501, are described in more
detail in Section 7.10.
7.10 Synchronization to input data bitstreams
After a reset, the SAA2501 mutes both sub-band and
baseband audio data. After data inputting has started, the
SAA2501 searches either for a sync pattern or a sync
pulse. The speed at which input data is read by the master
input to search for synchronization is described below. If
the application is such that the SAA2501 starts at a
random moment in time compared to the bitstream,
maximal one frame is skipped before a synchronization
pattern or pulse is encountered.
When the SAA2501 has detected the first synchronization
word or pulse, a number of frames are decoded in order to
verify synchronization; the input data for these frames is
read and decoded, but meanwhile the audio output is
muted. The number of muted frames depends on the input
data format (ISO/MPEG or EU147), whether the
ISO/MPEG Cyclic Redundancy Check (CRC) is active,
and whether the bit rate is free format. If the
synchronization is found to be false, the SAA2501
resumes the initial synchronization as described above. If
the detected pulse/pattern is concluded to be a real
synchronization pulse/pattern, Table 3 indicates the
number of muted frames.
January 1995
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