SAA2501 Datasheet, PDF (21/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
pair. Signal FDEF being HIGH indicates muting of FDAO
due to input data errors (see Fig.13).
FDEF can only change value at each FDFSY leading
edge, i.e. after each 384 sample periods (ISO/MPEG
layer I input data) or 1152 sample periods (ISO/MPEG
layer II input data): only whole frames are marked to be
correct or muted. As shown in detail in Fig.13, transitions
of FDFSY and FDEF take place one SCK period before a
trailing edge of WS.
The optionally processed sub-band data FDAI must be
synchronous to SCK and WS. Furthermore, the sub-band
index of the FDAI samples must be synchronized to
FDFSY: a sub-band logic 0 sample pair must be input
when FDFSY is HIGH (as shown in Fig.12). This means
that the delay of the external processing is allowed to be
any integer multiple of 32 sample periods. If no external
processing is to be applied, FDAO must be input back
directly to FDAI.
7.19 The baseband output interface
The decoded baseband audio data is output in an I²S-like
format (see Fig.14).
The output interfacing consists of 3 signals (see Table 11).
handbook, full pagewidth
WS
FDFSY
FDEF
1
2
3
4
384 (layer I)
1152 (layer II) 1
2
WS
FDFSY
FDEF
SCK
WS
FDFSY
FDEF
SCK
MLC401
Fig.13 Filter data error flag (FDEF) timing.
January 1995
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