SAA2501 Datasheet, PDF (38/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 37 Requirements for addressing mode timing (see Fig.19)
SYMBOL
t_d1
t_cL
t_cH
t_su1
t_h1
t_h2
PARAMETER
L3CLK HIGH to L3CLK LOW delay time after L3MODE LOW
L3CLK LOW time
L3CLK HIGH time
L3DATA set-up time before L3CLK HIGH
L3DATA hold time after L3CLK HIGH
L3CLK hold time before L3MODE HIGH
8.1.5.2 Data mode
andbook, full pagewidth
L3MODE
L3CLK
L3DATA
microcontroller
to IC
L3DATA
IC to
microcontroller
td2
t _d1
t _cL
t _cH
t _su
t _h1
th3
td3
td4
Fig.20 Data mode timing.
REQUIREMENT
≥190
≥250
≥250
≥190
≥30
≥190
UNIT
ns
ns
ns
ns
ns
ns
th2
td5
MGB508
Table 38 Requirements for data mode timing (see Fig.20)
SYMBOL
PARAMETER
t_d1
L3CLK HIGH to L3CLK LOW delay time after L3MODE HIGH
t_cL
L3CLK LOW time
t_cH
L3CLK HIGH time
Microcontroller to slave device
t_su1
L3DATA set-up time before L3CLK HIGH
t_h1
L3DATA hold time after L3CLK HIGH
t_h2
L3CLK hold time before L3MODE HIGH
Slave device to microcontroller
t_d2
L3DATA enable time after L3MODE HIGH
t_d3
L3DATA stable time after L3MODE HIGH
t_h3
L3DATA hold time after L3CLK HIGH
t_d4
L3DATA stable time after L3CLK HIGH
t_d4
L3DATA stable time after L3CLK HIGH between bit 7 of a byte and
bit 0 of next byte if no halt mode is used
t_d5
L3DATA disable time after L3MODE LOW
REQUIREMENT
≥190
≥250
≥250
≥190
≥30
≥190
0 < t_d2 ≤ 50
≤380
≥50
≤360
≤530
0 < t_d5 ≤ 50
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
January 1995
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