SAA2501 Datasheet, PDF (16/52 Pages) NXP Semiconductors – Digital Audio Broadcast DAB decoder

Philips Semiconductors
Digital Audio Broadcast (DAB) decoder
Preliminary specification
SAA2501
Table 8 Signals of coded data slave input interface
SIGNAL
CDS
CDSEF
CDSCL
CDSWA
CDSSY
DIRECTION
input
input
input
input
input
FUNCTION
ISO/MPEG or EU147 coded input data (slave input)
coded data (slave input) error flag
coded data (slave input) bit clock
coded data (slave input) burst window signal
coded data (slave input) frame sync
handbook, full pagewidth
CDS
CDSCL
CDSWA
CDSSY
CDSEF
valid data
frame start
1 unreliable data bit (example)
valid but unreliable data
invalid data
MGB496
CDSSY indicates frame start during valid data.
Fig.8 Input data serial transfer format (slave input).
CDS is the SAA2501 input data bitstream. Data clock
CDSCL must have a frequency equal to or higher than the
bit rate. The maximum CDSCL frequency is 768 kHz. Error
flag CDSEF is handled in the same way as CDMEF is
handled for the master input (in Fig.8, one unreliable data
bit is shown as an example). The value of CDSEF is
neglected for those bits where CDSWA is LOW. Window
signal CDSWA being HIGH indicates valid data; in this
way, burst input data is allowed. The constraints for the
ability to use ‘burst signals’ are explained later in this
Section 7.17.2. Frame sync signal CDSSY indicates the
start of each input data frame. CDSSY is synchronous with
CDSCL. CDSSY may be present or not: as described later
in this Section 7.17.2. The first valid CDS bit after a leading
edge of CDSSY is interpreted to be the first frame bit.
The minimum time for CDSSY to stay HIGH is one CDSCL
period; the maximum HIGH period is constrained by the
requirement that CDSSY must be LOW at least during one
CDSCL period per frame (a leading edge, i.e. a frame start
indication, must be present every frame). Leading edges
of CDSSY can occur while CDSWA is HIGH, as in Fig.8.
Alternatively, a situation as shown in Fig.9 is also allowed,
where CDSSY has a leading edge while CDSWA is LOW,
i.e. during invalid data. The first CDS bit after CDSWA
going HIGH is now interpreted to be the first frame bit.
January 1995
16