OXCF950_06 Datasheet, PDF (8/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
3 PIN DESCRIPTIONS
OXCF950 rev B DATA SHEET
TQFP Pin Number (TFBGA ball) Dir¹
CF/PCMCIA Interface and Control
46, 45, 43, 42
I
(D4, A2, A3, B3)
6, 7, 10, 11, 12, 37, 38, 41
I/O
(E2, E1, F1, F3, G1, A6, B5, A4)
44 (C3)
IU
5 (D1)
IU
4 (D2)
I
1 (B1)
I
3 (C1)
IU
2 (C2)
IU
32 (C5)
O
O
O
47 (B2)
IU
48 (A1)
O
UART / Local Bus Function
24 (H6)
O
23 (G5)
I
29 (E6)
I
26 (F5)
O
25 (G6)
O
27 (F6)
I
DS-0027 Feb 06
Name
Description
A[3:0]
PCMCIA/CF address bus, bits [3:0]
D[7:0]
PCMCIA/CF data bi-directional bus.
REG#
CE[1]#
OE#
WE#
IORD#
IOWR#
WP
Register select and I/O enable
Active low card enable
Active low memory read enable
Active-low write enable used for strobing Memory Write data
(Attribute memory).
Active-low I/O read enable
Active-low I/O write enable
Write protect (in Memory only mode)
IOIS16#
Data is 16 bit (in IO and Memory mode)
INT
RESET
READY#
C950 Mode:Active-high interrupt request
PCMCIA/CF Reset
Device ready (in Memory only mode)
IREQ#
Active-low Interrupt request (in C950, IO and Memory mode).
SOUT
UART serial data output.
IrDA_Out
SIN
UART IrDA data output when MCR[6] is set in enhanced
mode.
UART serial data input.
IrDA_In
DCD#
DTR#
UART IrDA data input when IrDA mode is enabled (see
above).
Active-low modem data-carrier-detect input.
Active-low modem data-terminal-ready output. If automated
DTR# flow control is enabled, the DTR# pin is asserted and
de-asserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
485_En
In RS485 half-duplex mode, the DTR# pin may be
programmed to reflect the state of the transmitter empty bit to
automatically control the direction of the RS485 transceiver
buffer (see register ACR[4:3]).
Tx_Clk_Out
RTS#
CTS#
Transmitter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmitter clock may
be asserted on the DTR# pin (see register CKS[5:4]).
Active–low modem request-to-send output. If automated
RTS# flow control is enabled, the RTS# pin is de-asserted
and reasserted whenever the receiver FIFO reaches or falls
below the programmed thresholds, respectively.
Active-low modem clear-to-send input. If automated CTS#
flow control is enabled, upon de-assertion of the CTS# pin,
External—Free Release
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