OXCF950_06 Datasheet, PDF (51/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
In 9-bit mode, in-band flow control is disabled regardless of
the setting of EFR[3:0] and the XON1/XON2/XOFF1 and
XOFF2 registers are used for special character detection.
Interrupts in 9-Bit Mode:
While IER[2] is set, upon receiving a character with status
error, a level 1 interrupt is asserted when the character and
the associated status are transferred to the FIFO.
The 950 can assert an optional interrupt if a received
character has its 9^th bit set. As multi-drop systems often
use the 9^th bit as an address bit, the receiver is able to
generate an interrupt upon receiving an address character.
This feature is enabled by setting NMR[2]. This will result
in a level 1 interrupt being asserted when the address
character is transferred to the receiver FIFO.
In this case, as long as there are no errors pending, i.e.
LSR[1], LSR[3], and LSR[4] are clear, '0' can be read back
from LSR[7] and LSR[1], thus differentiating between an
‘address’ interrupt and receiver error or overrun interrupt in
9-bit mode. Note however that should an overrun or error
interrupt actually occur, an address character may also
reside in the FIFO. In this case, the software driver should
examine the contents of the receiver FIFO as well as
process the error.
The above facility produces an interrupt for recognizing any
‘address’ characters. Alternatively, the user can configure
950 core to match the receiver data stream with up to four
programmable 9-bit characters and assert a level 5
interrupt after detecting a match. The interrupt occurs when
the character is transferred to the FIFO (See below).
NMR[0]: 9-bit mode enable
logic 0 ⇒ 9-bit mode is disabled.
logic 1 ⇒ 9-bit mode is enabled.
NMR[1]: Enable interrupt when 9^th bit is set
logic 0 ⇒ Receiver interrupt for detection of an
‘address’ character (i.e. 9^th bit set) is
disabled.
logic 1 ⇒ Receiver interrupt for detection of an
‘address’ character (i.e. 9^th bit set) is
enabled and a level 1 interrupt is asserted.
Special Character Detection
While the UART is in both 9-bit mode and Enhanced mode,
setting IER[5] will enable detection of up to four ‘address’
characters. The least significant eight bits of these four
programmable characters are stored in special characters
1 to 4 (XON1, XON2, XOFF1 and XOFF2 in 650 mode)
registers and the 9^th bit of these characters are
programmed in NMR[5] to NMR[2] respectively.
NMR[2]: Bit 9 of Special Character 1
NMR[3]: Bit 9 of Special Character 2
NMR[4]: Bit 9 of Special Character 3
NMR[5]: Bit 9 of Special Character 4
NMR[7:6]: Reserved
Bits 6 and 7 of NMR are always cleared and reserved for
future use.
6.11.10 Modem Disable Mask ‘MDM’
The MDM register is located at offset 0x0E of the ICR
This register is cleared after a hardware reset to maintain
compatibility with 16C550. It allows the user to mask
interrupts and control sleep operation due to individual
modem lines or the serial input line.
MDM[0]: Disable delta CTS
logic 0 ⇒ Delta CTS is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta CTS
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta CTS is disabled. It can not generate an
interrupt or wake up the UART.
MDM[1]: Disable delta DSR
logic 0 ⇒ Delta DSR is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DSR
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta DSR is disabled. In can not generate an
interrupt or wake up the UART.
MDM[2]: Disable Trailing edge RI
logic 0 ⇒ Trailing edge RI is enabled. It can generate a
level 4 interrupt when enabled by IER[3].
Trailing edge RI can wake up the UART when it
is asleep under auto-sleep operation.
logic 1 ⇒ Trailing edge RI is disabled. In can not generate
an interrupt or wake up the UART.
MDM[3]: Disable delta DCD
logic 0 ⇒ Delta DCD is enabled. It can generate a level 4
interrupt when enabled by IER[3]. Delta DCD
can wake up the UART when it is asleep under
auto-sleep operation.
logic 1 ⇒ Delta DCD is disabled. In can not generate an
interrupt or wake up the UART.
MDM[7:4]: Reserved
These bits must be set to ‘0000’
6.11.11 Readable FCR ‘RFC’
The RFC register is located at offset 0x0F of the ICR
This read-only register returns the current state of the FCR
register (Note that FCR is write-only). This register is
included for diagnostic purposes.
DS-0027 Feb 06
External—Free Release
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