OXCF950_06 Datasheet, PDF (35/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers
via ICR. Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Control Registers use the following procedure.
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 1112).
Write the desired value to ICR (address 1012).
Reading from ICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxx2 to address 1012. Ensure that other bits in ACR are not changed.
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 1112).
Read the desired value from ICR (address 1012).
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxx2 to ICR, thus enabling access to standard registers again.
6.3 Reset Configuration
6.3.1 Host Reset
After a hardware reset or soft reset (bit 7 of COR register),
all writable registers are reset to 0x00, with the following
exceptions:
1. DLL which is reset to 0x01.
2. CPR is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 00000002
TFL[6:0]: 00000002
LSR[7:0]: 0x60 signifying that both the transmitter and the
transmitter FIFO are empty
MSR[3:0]: 00002
MSR[7:4]: Dependent on modem input lines DCD, RI, DSR
and CTS respectively
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx000002
RFC[7:0]: 000000002
GDS[7:0]: 000000012
6.4 Transmitter & Receiver FIFOs
DMS[7:0]: 000000102
CKA[7:0]: 000000002
The reset state of output signals for are tabulated below:
Signal
SOUT
RTS#
DTR#
Reset state
Inactive High
Inactive High
Inactive High
Table 28: Output Signal Reset State
6.3.2 Software Reset
An additional feature available in the 950 core is software
resetting of the serial channel. The software reset is
available using the CSR register. Software reset has the
same effect as a hardware reset except it does not reset
the clock source selections (i.e. CKS register and CKA
register). To reset the UART write 0x00 to the Channel
Software Reset register ‘CSR’.
Both the transmitter and receiver have associated holding
registers (FIFOs), referred to as the transmitter holding
register (THR) and receiver holding register (RHR)
respectively.
In normal operation, when the transmitter finishes
transmitting a byte it will remove the next data from the top
of the THR and proceed to transmit it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmitted has been completed
(i.e. the transmitter shift register is empty) the transmitter is
said to be idle. Similarly, when the receiver finishes
receiving a byte, it will transfer it to the bottom of the RHR.
If the RHR is full, an overrun condition will occur (see
section 6.5.3).
Data is written into the bottom of the THR queue and read
from the top of the RHR queue completely asynchronously
to the operation of the transmitter and receiver.
DS-0027 Feb 06
External—Free Release
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