OXCF950_06 Datasheet, PDF (11/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
4 CONFIGURATION & OPERATION
4.1 Mode Selection
The OXCF950 has four default modes of operation, as
shown in the table below.
MODE pin
0
1
0
1
EE_DI pin
0
0
‘1’ or to external
EEPROM
‘1’ or to external
EEPROM
Operation
‘Generic’ Normal mode
with 3 address bits
decoded for I/O
16C950 mode
(standard local bus type
UART)
‘Normal’ mode with 4
address bits decoded
for I/O
‘Local Bus’ mode with 4
address bits decoded
for I/O
Table 2: Default Modes of Operation
4.1.1 Generic Mode
Generic Mode is compatible with PCMCIA and CF host
systems. It is the same as ‘Normal’ mode, except that
when I/O accesses take place, only the bottom 3 bits of the
address range are decoded. Similarly the Card Information
Structure indicates an I/O range of 8 locations. This mode
allows generic drivers to locate the UART on a default 8-
byte boundary. In this mode access to the configuration
registers is performed via paging. Generic mode address
decoding can also be selected by EEPROM configuration.
4.1.2 16C950 Mode
This mode is provided for non PCMCIA/CF applications. In
this mode all the PCMCIA/CF decoding, CIS and EEPROM
sections of the design are bypassed and the CF950 acts as
a local-bus style device. To implement this mode -
REG#, EE_DI should be tied to GND,
OE#, WE#, MODE should be tied to VDD.
The user can use A3 to access configuration registers to
allow control of MIO pins and the clock divider. For most
applications, however, A3, MIO1 and MIO0 should also be
tied to GND.
CE1#, IORD#, IOW# and A[2..0] then become the local bus
chip-select and read, write, address access controls.
IREQ# becomes an active-high interrupt output, and
IOIS16# becomes an active-low interrupt output.
4.1.3 Normal/Local Bus Modes
These modes are identical to the previous CF950 modes of
operation. They are suitable for PCMCIA/CF host systems.
4.2 PCMCIA/CF Operation
PCMCIA and CF host systems allow for hot insertion of
cards.
Once a card has been inserted into a host system, the host
system will configure it. The PCMCIA standard defines two
card detect pins, that allow the host to be notified when a
card is inserted or removed.
By default the device will power up in either Normal or
Local Bus mode, depending on the mode pin (and the
EE_DI pin for ‘Generic’ mode). The difference between
these two modes is given in the following table. Note that
the Local Bus mode is not suitable for CF systems.
Normal Mode (MODE=0)
Address bus is 8 bits wide.
Indirect access is not used.
No external local bus.
Local Bus Mode (MODE=1)
Address bus is 4 bits wide.
Indirect access is used.
External local bus supported.
Table 3: Differences between Normal & Local Bus Mode
The host system will wait for the READY# signal to be
active before reading the Card Information Structure, given
in attribute memory within the device. By reading this tuple
information, the host system is able to identify the device
type and the necessary resources requested by the device.
The host system will then load the device-driver software
according to this information and will configure the IO,
memory and interrupt resources. After determining that the
device is a memory and IO type device the host will enable
it’s IO mode by writing to the device’s Configuration
Options Register in attribute memory space. Device
drivers can then access the functions at the assigned
addresses.
A set of local configuration registers have been provided
that can be used to control the device’s characteristics
(such as interrupt handling) and report internal functional
status. These registers can be accessed in IO space,
utilising the same IO space as the local bus (Local Bus
mode only) and are situated above the UART registers.
These local registers can be set up by device drivers or
from the optional EEPROM. In generic mode, the
DS-0027 Feb 06
External—Free Release
Page 11 of 66