OXCF950_06 Datasheet, PDF (47/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
CLOCK
VDD
XTLI
Figure 6: Clock Module Connectivity
6.10.6 External 1x Clock Mode
The transmitter and receiver can accept an external clock
applied to the RI# and DSR# pins respectively. The clock
options are selected using the clock select register (CKS -
see section 6.11.8). The transmitter and receiver may be
configured to operate in 1x (Isochronous) mode by setting
CKS[7] and CKS[3], respectively. In Isochronous mode,
transmitter or receiver will use the 1x clock (usually but not
necessarily an external source) where asynchronous
framing is maintained using start, parity and stop-bits.
However serial transmission and reception is synchronised
to the 1x clock. In this mode asynchronous data may be
transmitted at baud rates up to 60Mbps. The local 1x clock
source can be asserted on the DTR# pin.
Note that line drivers need to be capable of transmission at
data rates twice the system clock used (as one cycle of the
system clock corresponds to 1 bit of serial data). Also note
that enabling modem interrupts is illegal in isochronous
mode, as the clock signal will cause a continuous change
to the modem status (unless masked in MDM register, see
section 6.11.10).
6.11 Additional Features
6.10.7 Crystal Oscillator Circuit
The OXCF950 may be clocked by a crystal connected to
XTLI and XTLO or directly from a clock source connected
to the XTLI pin. The circuit required to use the on-chip
oscillator is shown below. Note the crystal circuit is only
suitable for operation up to 20 MHz.
XTLO
R₂
C₁
R₁
XTLI
C₂
Figure 7: Crystal Oscillator Circuit
Frequency
Range
(MHz)
1.8432 – 8
8-20
C1 (pF)
68
33-68
C2 (pF)
22
33 – 68
R1 (Ω)
220K
220K-2M2
R2 (Ω)
470R
470R
Table 39: Component Values
Note: For better stability use a smaller value of R1. Increase
R1 to reduce power consumption.
The total capacitive load (C1 in series with C2) should
be that specified by the crystal manufacturer (nominally
16pF)
6.11.1 Additional Status Register ‘ASR’
ASR[0]: Transmitter disabled
logic 0 ⇒ The transmitter is not disabled by in-band flow
control.
logic 1 ⇒ The receiver has detected an XOFF, and has
disabled the transmitter.
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the transmitter if it was disabled by in-band
flow control. Writing a 1 to this bit has no effect.
ASR[1]: Remote transmitter disabled
logic 0 ⇒ The remote transmitter is not disabled by in-
band flow control.
logic 1 ⇒ The transmitter has sent an XOFF character,
to disable the remote transmitter. (Cleared
when a subsequent XON is sent).
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the remote transmitter (an XON is
transmitted). Writing a 1 to this bit has no effect.
Note: The remaining bits (ASR[7:2]) of this register are read only
ASR[2]: RTS
This is the complement of the actual state of the RTS# pin
when the device is not in loopback mode. The driver
software can determine if the remote transmitter is disabled
by RTS# out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR# pin
when the device is not in loopback mode. The driver
software can determine if the remote transmitter is disabled
by DTR# out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pin’s actual state.
DS-0027 Feb 06
External—Free Release
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