OXCF950_06 Datasheet, PDF (17/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
UART Divider/Interrupt Pulse Width Divider register ‘DIV’ (Offset 0x0A)
This register defines the divide values (2^N division) for the clocks to the UART and Interrupt pulse generator signal. This allows
the device to be set up in its lowest power mode possible, and is fully programmable by the host or the EEPROM. The default
value for the UART clock divider provides a clock to the UART of x1. The default value for the Interrupt pulse divider provides a
clock to the interrupt processor of /32. See Section 5.4.1 Note that the UART clock rate should not be changed without then
resetting the UART(see SRT register).
Bits
Description
7:6
Reserved
5:3
Uart clock divide value.
The division ratio is 2^N, giving 1, 2, 4, 8, 16, 32, 64, 128
2:0
Interrupt Pulse divide value:
This field should be set under the following clock freq. conditions
000 -> when clock frequency is less than 2MHz
001 -> when clock frequency is between 2 and 4MHz
010 -> when clock frequency is between 4 and 8MHz
011 -> when clock frequency is between 8 and 16MHz
100 -> when clock frequency is between 16 and 32MHz
101 -> when clock frequency is between 32 and 64MHz
110 -> RESERVED
111 -> RESERVED
Read/Write
EEPROM PCMCIA
-
R
W
R/W
Reset
00
000
W
R/W
101
Table 9: UART Divider/ Interrupt Pulse Width Divider
Mode Status register ‘MSR’ (Offset 0x0B)
This read only register return the state of the MODE pin (i.e. whether in Normal or Local Bus modes).
Bits
Description
7:1
Reserved
0
Mode
O = Normal, 1 = Local Bus
Table 10: Mode Status Register
Read/Write
EEPROM PCMCIA
-
R
-
R
Reset
0000000
X
DS-0027 Feb 06
External—Free Release
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