OXCF950_06 Datasheet, PDF (30/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
6 INTERNAL 950 UART
The internal UART within the OXCF950 is based on the 16C950 rev B, and is henceforth referred to as the 950 core. Some
modes of the 16C950 rev B that are configured by pin options such as Extended-550 mode are not available in this embedded
core.
6.1 Mode Selection
The 950 core is software compatible with the 16C450, 16C550, 16C654 and 16C750 UARTs. The operation of the 950 depends
on a number of mode settings. These modes are referred to throughout this data sheet. The FIFO depth and compatibility modes
are tabulated below:
UART Mode FIFO FCR[0] Enhanced mode
FCR[5]
size
(EFR[4]=1) (guarded with LCR[7] = 1)
450
1
0
X
X
550
16
1
0
0
650
128
1
1
X
750
128
1
0
1
950*
128
1
1
X
Table 23: UART Mode Configuration
* Note that 950 mode configuration is identical to 650 configuration
6.1.1 450 Mode
After a hardware reset bit 0 of the FIFO Control Register
(‘FCR’) is cleared, hence the 950 is compatible with the
16C450. The transmitter and receiver FIFOs (referred to as
the ‘Transmit Holding Register’ and ‘Receiver Holding
Register’ respectively) have a depth of one. This is referred
to as ‘Byte mode’. When FCR[0] is cleared, all other mode
selection parameters are ignored.
6.1.2 550 Mode
After a hardware reset, writing a 1 to FCR[0] will increase
the FIFO size to 16, providing compatibility with 16C550
devices.
6.1.3 750 Mode
Writing a 1 to FCR[0] will increase the FIFO size to 16. In a
similar fashion to 16C750, the FIFO size can be further
increased to 128 by writing a 1 to FCR[5]. Note that access
to FCR[5] is protected by LCR[7]. I.e., to set FCR[5],
software should first set LCR[7] to temporarily remove the
guard. Once FCR[5] is set, the software should clear
LCR[7] for normal operation.
The 16C750 additional features over the 16C550 are
available as long as the UART is not put into Enhanced
mode (i.e. EFR[4] should be ‘0’). These features are:
1. Deeper FIFOs
2. Automatic RTS/CTS out-of-band flow control
3. Sleep mode
6.1.4 650 Mode
The 950 is compatible with the 16C650 when EFR[4] is set,
i.e. the device is in Enhanced mode. As 650 software
drivers usually put the device into Enhanced mode, running
650 drivers on the 950 will result in 650 compatibility with
128 deep FIFOs, as long as FCR[0] is set. Note that the
650 emulation mode of the 950 provides 128 byte deep
FIFOs whereas the standard 16C650 has only 32 byte
FIFOs.
650 mode has the same enhancements as the 16C750
over the 16C550, but these are enabled using different
registers.
There are also additional enhancements over those of the
16C750 in this mode, these are:
1. Automatic in-band flow control
2. Special character detection
3. Infra-red “IrDA-format” transmit and receive mode
4. Transmit trigger levels
5. Optional clock prescaler
6.1.5 950 Mode
The additional features offered in 950 mode generally only
apply when the UART is in Enhanced mode (EFR[4]=’1’).
Provided FCR[0] is set, in Enhanced mode the FIFO size is
128.
Note that 950 mode configuration is identical to that of 650
mode, however additional 950 specific features are
DS-0027 Feb 06
External—Free Release
Page 30 of 66