OXCF950_06 Datasheet, PDF (36/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one byte at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
Data written to the THR when it is full is lost. Data read
from the RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Register ‘LSR’ (see section 6.5.3). Interrupts can be
generated or DMA signals can be used to transfer data
to/from the FIFOs. The number of items in each FIFO may
also be read back from the transmitter FIFO level (TFL)
and receiver FIFO level (RFL) registers (see section
6.11.2).
6.4.1 FIFO Control Register ‘FCR’
FCR[0]: Enable FIFO mode
logic 0 ⇒ Byte mode.
logic 1 ⇒ FIFO mode.
This bit should be enabled before setting the FIFO trigger
levels.
FCR[1]: Flush RHR
logic 0 ⇒ No change.
logic 1 ⇒ Flushes the contents of the RHR
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
FCR[2]: Flush THR
logic 0 ⇒ No change.
logic 1 ⇒ Flushes the contents of the THR, in the same
manner as FCR[1] does for the RHR.
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable
logic 0 ⇒ DMA mode '0'.
logic 1 ⇒ DMA mode '1'.
650 mode:
In 650 mode the transmitter interrupt trigger levels are set
to the following values:
FCR[5:4]
00
01
10
11
Transmit Interrupt Trigger level
16
32
64
112
Table 29: Transmit Interrupt Trigger Levels
These levels only apply when in Enhanced mode and in
DMA mode 1 (FCR[3] = 1), otherwise the trigger level is set
to 1. A transmitter empty interrupt will be generated (if
enabled) if the TFL falls below the trigger level.
750 Mode:
In 750 compatible non-Enhanced (EFR[4]=0) mode,
transmitter trigger level is set to 1, FCR[4] is unused and
FCR[5] defines the FIFO depth as follows:
FCR[5]=0 Transmitter and receiver FIFO size is 16 bytes.
FCR[5]=1 Transmitter and receiver FIFO size is 128 bytes.
In non-Enhanced mode FCR[5] is only writable when
LCR[7] is set. Note that in Enhanced mode, the FIFO size
is also increased to 128 bytes when FCR[0] is set.
950 mode:
Setting ACR[5]=1 enables arbitrary transmitter trigger level
setting using the TTL register (see section 6.11.4), hence
FCR[5:4] are ignored.
FCR[7:6]: RHR trigger level
In 550, extended 550, 650 and 750 modes, the receiver
FIFO trigger levels are defined using FCR[7:6]. The
interrupt trigger level and upper flow control trigger level
where appropriate are defined by L2 in the table below. L1
defines the lower flow control trigger level where
applicable. Separate upper and lower flow control trigger
levels introduce a hysteresis element in in-band and out-of-
band flow control (see section 6.9).
DMA signals are not bonded out in the OXCF950, so this
control only affects the transmitter trigger level in DMA
mode 0.
FCR[5:4]: THR trigger level
Generally in 450, 550, extended 550 and 950 modes these
bits are unused (see section 6.1 for mode definition). In
650 mode they define the transmitter interrupt trigger levels
and in 750 mode FCR[5] increases the FIFO size.
FCR
Mode
[7:6]
650
750
FIFO Size 128 FIFO Size 128
L1 L2 L1 L2
00 1 16 1
1
01 16 32 1 32
10 32 112 1 64
11 112 120 1 112
550
FIFO Size 16
L1 L2
n/a 1
n/a 4
n/a 8
n/a 14
450, 550 and extended 550 modes:
The transmitter interrupt trigger levels are set to 1 and
FCR[5:4] are ignored.
Table 30: Receiver Trigger Levels
In Byte mode (450 mode) the trigger levels are all set to 1.
DS-0027 Feb 06
External—Free Release
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