OXCF950_06 Datasheet, PDF (4/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
6.4 TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 35
6.4.1 FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 36
6.5 LINE CONTROL & STATUS............................................................................................................................................. 37
6.5.1 FALSE START BIT DETECTION.................................................................................................................................. 37
6.5.2 LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 37
6.5.3 LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 37
6.6 INTERRUPTS & SLEEP MODE........................................................................................................................................ 39
6.6.1 INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 39
6.6.2 INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 40
6.6.3 INTERRUPT DESCRIPTION ........................................................................................................................................ 40
6.6.4 SLEEP MODE ............................................................................................................................................................... 41
6.7 MODEM INTERFACE ....................................................................................................................................................... 41
6.7.1 MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 41
6.7.2 MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 42
6.8 OTHER STANDARD REGISTERS ................................................................................................................................... 42
6.8.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 42
6.8.2 SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 42
6.9 AUTOMATIC FLOW CONTROL....................................................................................................................................... 42
6.9.1 ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 42
6.9.2 SPECIAL CHARACTER DETECTION .......................................................................................................................... 43
6.9.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 44
6.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 44
6.10 BAUD RATE GENERATION............................................................................................................................................. 44
6.10.1 GENERAL OPERATION ............................................................................................................................................... 44
6.10.2 CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 45
6.10.3 TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 45
6.10.4 INPUT CLOCK OPTIONS ............................................................................................................................................. 46
6.10.5 TTL CLOCK MODULE .................................................................................................................................................. 46
6.10.6 EXTERNAL 1X CLOCK MODE..................................................................................................................................... 47
6.10.7 CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 47
6.11 ADDITIONAL FEATURES ................................................................................................................................................ 47
6.11.1 ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 47
6.11.2 FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 48
6.11.3 ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 48
6.11.4 TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 49
6.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 49
6.11.6 FLOW CONTROL LEVELS ‘FCL & FCH’...................................................................................................................... 49
6.11.7 DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 50
6.11.8 CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 50
6.11.9 NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 50
6.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 51
6.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 51
6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 52
6.11.13 DMA STATUS REGISTER ‘DMS’ ................................................................................................................................. 52
6.11.14 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 52
6.11.15 CLOCK ALTERATION REGISTER ‘CKA’ ..................................................................................................................... 52
6.11.16 MISC DATA REGISTER ............................................................................................................................................... 52
7 SERIAL EEPROM SPECIFICATION ................................................................................................... 53
7.1 EEPROM DATA ORGANISATION ................................................................................................................................... 53
7.2 ZONE 0: HEADER ............................................................................................................................................................ 53
7.3 ZONE 1: CARD INFORMATION STRUCTURE................................................................................................................ 54
7.4 ZONE 2: LOCAL REGISTER CONFIGURATION ............................................................................................................ 54
7.5 ZONE 3: FUNCTION ACCESS (UART)............................................................................................................................ 55
8 OPERATING CONDITIONS................................................................................................................. 56
9 DC ELECTRICAL CHARACTERISTICS ............................................................................................. 57
DS-0027 Feb 06
External—Free Release
Page 4 of 66