OXCF950_06 Datasheet, PDF (18/66 Pages) Oxford Semiconductor – low cost asynchronous 16-bit PC card or Compact Flash UART device

OXFORD SEMICONDUCTOR, INC.
OXCF950 rev B DATA SHEET
Interrupt Status and Control register ‘ISR’ (Offset 0x0C)
This register controls the assertion of interrupts from the User I/O pins (MIO[1:0]) as well as returning the internal status of the
interrupt sources.
Bits
Description
Read/Write
Reset
EEPROM PCMCIA
7:5
Reserved
-
R
000
4
UART Interrupt status
-
R
0
This bit reflects the state of the internal UART interrupt
3
MIO[1] interrupt mask
W
R/W
0
When set to ‘1’ allows pin MIO[1] to assert an interrupt on the devices
IREQ# pin. The state of the MIO[1] signal that causes an interrupt is
dependent upon the polarity set by the register fields MIC[3:2].
2
MIO[0] interrupt mask
W
R/W
0
When set to ‘1’ allows pin MIO[0] to assert an interrupt on the devices
IREQ# pin. The state of the MIO[0] signal that causes an interrupt is
dependent upon the polarity set by the register fields MIC[1:0].
1
MIO1 Internal state
-
R
X
This bit reflects the state of the internal MIO[1]. The internal MIO[1] signal
reflects the non-inverted or inverted state of MIO[1] pin
0
MIO0 Internal state
-
R
X
This bit reflects the state of the internal MIO[0]. The internal MIO[0] signal
reflects the non-inverted or inverted state of MIO[0] pin
Table 11: Interrupt Status Register
Soft UART/Local Bus reset register ‘SRT’ (Offset 0x0D)
This register controls the soft reset passed to the UART and local bus reset. These reset lines are in addition to the soft reset
that may be produced by the host (bit[7] of the COR register in attribute memory space). Note that the local bus reset is used in
Local Bus mode only and not in Normal mode. Note these bits are not self-clearing.
Bits
Description
7:2
Reserved
1
Active high soft reset for UART
0
Active high soft reset for Local Bus
Read/Write
EEPROM PCMCIA
-
R
W
R/W
W
R/W
Reset
000000
0
0
Table 12: Soft UART / Local Bus Reset (LB reset used in Local Bus Mode only)
Generic Mode Control register ‘GMC’ (Offset 0x0E)
This register provides EEPROM control for the pin-selectable Generic mode. When set, only the bottom 3 address bits are
decoded for UART access, and paging is required to switch to configuration registers. It is up to the user to ensure the CIS tuples
also request only an 8 bit address range if this is programmed via the EEPROM (i.e. CIS entries will be needed as well).
Bits
Description
Read/Write
Reset
EEPROM PCMCIA
0
Generic Mode Address Decode
W
R
0
Enables Generic Mode decoding when ‘1’. This should only be set in
Normal mode (MODE = ‘0’)
This feature is new to OXCF950 rev B
Table 13: Generic Mode Control
DS-0027 Feb 06
External—Free Release
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