LC89091JA Datasheet, PDF (8/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
8. System Settings
8.1 Power-On Reset
 The LC89091JA features a built-in power-on reset circuit, and constantly monitors the power supply status.
<100ms
>150s
>1s
VDD
Internal reset
1/2VDD
Reset state
Figure 8.1: Power-On Reset Timing
Pin No.
3
4
6
9
Port Name
ERR
GPO
MPIO
MCKO
Table 8.1: Output Port State Immediately after Power-On Reset
Output State
Pin No.
Port Name
Output State
H output
10
BCKO
XIN/4 input clock output (6.144MHz)
L output (Non-PCM flag)
11
LRCKO
XIN/256 input clock output (96kHz)
Hi-Z output (Emphasis flag)
12
DATAO
SDIN input data output
XIN input clock output (24.576MHz)
14
XOUT
XIN invert output
8.2 Register Reset and Power-Down Mode
 The SYSRST register resets circuits other than register.
 During reset period, register setting state hold and can also change.
 Although a system is reset by SYSRST register, the oscillation amplifier operates, and the clock is output to MCKO,
BCKO and LRCKO pins. But, DATAO pin outputs "L" without relation to the setup.
 The system is set power-down mode by PDMODE register.
 During power-down mode period, register setting state hold and can also change.
 In power-down mode, the circuits expect a power-on reset and a microcontroller interface will be set to stop condition
all the circuit operations, and the clock is not output.
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