LC89091JA Datasheet, PDF (10/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
8.5 Clocks
8.5.1 Master Clock
 The clock source is selected between the following two master clocks.
1) PLL source: 512fs
2) XIN source: 24.576MHz
8.5.2 PLL Source Master Clock
 The PLL synchronizes with the input S/PDIF and outputs 512fs clock.
 The PLL clock is controlled by PLLACC, PLLDIV[1:0] and PRSEL[1:0] register settings.
 Normally, "PLLACC=0" is set and PLL clock is output for each input sampling frequency band. At this setting,
output clock frequency fluctuation by varying the sampling frequency is kept to a narrow band, such as 512fs output
when fs=32kHz to 48kHz, 256fs output when fs=64kHz to 96kHz, and 128fs output when fs=128kHz to 192kHz.
 When "PLLACC=0" is set, the PLL clock is set with the PLLDIV[1:0] register
 When "PLLACC=0" is set, during the PLL is locked, switching is not performed even when the PLLDIV[1:0] register
setting is changed. These registers switching are executed when the PLL is in unlocked status. This setting becomes
valid after the PLL is locked again.
 To set an output clock that does not depend on the S/PDIF input sampling frequency, "PLLACC=1" is set. At this
setting, the clock frequency is always multiplied by a constant and output, such as output at 256fs for all sampling
frequencies from 32kHz to 192kHz.
 When "PLLACC=1" is set, the PLL clock is set with the PRSEL[1:0] register.
 When "PLLACC=1" is set, PRSEL[1:0] register can be changed even PLL lock state.
 The change to "PLLACC=1" from "PLLACC=0" is possible even PLL lock state. But, the setting change to
"PLLACC=0" from "PLLACC=1" becomes valid after the PLL is locked again.
 The PLL output clock setting flow is shown below.
S/PDIF Input
512fs
Lock detection
Lock
Fs calculation
Unlock
PLL output
Free- run
“PLLACC”
1
0
Fs=
No
32k,44.1k,48k
Yes
“PLLDIV”
00 or 10
01 or 11
PLL output
256fs
PLL output
512fs
PLL fixation output
“PRSEL=00”: 256fs
“PRSEL=01”: 512fs
“PRSEL=10”: 128fs
Fs=
No
64k,88.2k,96k
Yes
“PLLDIV”
00 or 01
10 or 11
PLL output
512fs
PLL output
256fs
Fs=
No
128k,176.4k,192k
Yes
PLL output
128fs
PLL output
256fs
Figure 8.4: PLL Output Clock Flow Diagram
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