LC89091JA Datasheet, PDF (16/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
8.7 Error Output Processing (ERR)
 The ERR output can be selected the following outputs by the ERRSEL register.
8.7.1 Lock Error and Data Error Output ("ERRSEL=0")
 The ERR pin outputs an error flag when PLL lock error or data error occurs.
 The ERR is output synchronizing with LRCKO and can be readout with the microcontroller interface.
8.7.1.1 PLL Lock Error
 The PLL gets unlocked for input data that lost bi-phase modulation regularity, or input data for which preambles B, M
and W cannot be detected.
 ^{However, even if preambles B, M and W are detected if the timing does not conform to the IEC60958, the PLL get}
unlocked and processed. For example, period of preamble B is not every192 frames.
 The ERR outputs "H" when the PLL lock error occurs.
 The ERR outputs "L" when the data demodulation returns normal and "H" is held for somewhere between 3m to 36ms.
 This holding time is set with the ERRWT register.
Table 8.4: ERR Release Maintenance Period after a PLL Locks
S/PDIF input sampling frequency
ERR release maintenance period after a PLL locks (ms)
(kHz)
"ERRWT=0"
"ERRWT=1"
32
18
36
44.1
13
26
48
12
24
88.2
6.5
13
96
6
12
176.4
3.3
6.5
192
3
6
8.7.1.2 Input Data Parity Error
 An odd number of errors among parity bits in input data and input parity errors are detected.
 The ERR outputs "H" when an input parity error occurs.
 When an input parity error occurs, output data is replaced to the data of one frame ago.
However, when having received non-PCM data, data does not replace. In this case, data including an error is output.
8.7.1.3 Other Errors
 Even if ERR turns to "L", the channel status bits of 24 to 27 (sampling frequency information) are always fetched and
the data of the previous block is compared with the current data. Moreover, the input data sampling frequency is
calculated from the fs clock extracted from the input data, and the fs calculated value is compared in the same way as
described above. If any difference is detected in these data, ERR is instantly made "H" and the same processing as for
PLL lock errors is carried out. In this case, the clock source is switched to XIN and processing is restarted at lock
status identification processing.
 In order to support sources with a variable fs (for example, a CD player with a variable pitch function), any change in
fs made after ERR is reset is not reflected on ERR unless such change exceeds the PLL capture range.
8.7.2 DATAO data Mute Signal Output ("ERRSEL=1")
 This mode outputs the state of the audio data outputted from the DATAO pin. (See “Figure 8.9”)
 A mute processing setup at the time of non-PCM audio data reception ("NPMODE=1")) is also reflected.
ERR output
L
H
Table 8.5: DATAO Output State Signal Output
DATAO output conditions
Muted
Outputted
No.A2172-16/30