LC89091JA Datasheet, PDF (25/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
01h
D7
Register name
"0"
Initial value
0
Setting
R
Address: 01h; Clock Setting
D6
D5
D4
D3
D2
D1
D0
"0"
XOUTCK
PRSEL1
PRSEL0
PLLDIV1
PLLDIV0
PLLACC
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
PLLACC
PLL clock lock frequency setting
0: Automatic control (initial value)
1: Manual setting
PLLDIV[1:0]
PLL lock time MCKO output setting when PLLACC is set to "0"
00: 512fs output: When receiving 32kHz, 44.1kHz, 48kHz (initial value)
256fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
01: 256fs output: When receiving 32kHz, 44.1kHz, 48kHz
256fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
10: 512fs output: When receiving 32kHz, 44.1kHz, 48kHz
512fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
11: 256fs output: When receiving 32kHz, 44.1kHz, 48kHz
512fs output: When receiving 64kHz, 88.2kHz, 96kHz
128fs output: When receiving 128kHz, 176.4kHz, 192kHz
PRSEL[1:0]
PLL lock time MCKO output setting when PLLACC is set to "1"
00: 256fs output (initial value)
01: 512fs output
10: 128fs output
11: Reserved
XOUTCK
XIN clock output setting when PLL is unlocked
0: MCKO=24.576MHz, BCKO=6.144MHz, LRCKO=96kHz (initial value)
1: MCKO=24.576MHz, BCKO=3.072MHz, LRCKO=48kHz
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