LC89091JA Datasheet, PDF (26/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
02h
Register name
Initial value
Setting
D7
NPMODE
0
R/W
D6
ERRSEL
0
R/W
Address: 02h; Data setting
D5
D4
D3
GPOSEL1
GPOSEL0
DATMUT
0
0
0
R/W
R/W
R/W
D2
THRSEL
0
R/W
D1
DINSEL
0
R/W
D0
DAFORM
0
R/W
DAFORM
Audio data output format setting
0: I²S data output (initial value)
1: 24-bit MSB first, left-justified data output
DINSEL
Data demodulation input setting
0: RXIN (initial value)
1: MPIO (when "MPSEL=1")
THRSEL
GPO output data setting when "GPOSEL[1:0]=01"
0: RXIN (initial value)
1: MPIO (when "MPSEL=1")
DATMUT
DATAO pin output setting
0: Output SDIN data while PLL is unlocked (initial value)
1: Mute, "L" output
GPOSEL[1:0]
GPO output data setting
00: Channel status bit 1 output (initial value)
01: Input S/PDIF through output
10: "L" output
11: "H" output
ERRSEL
ERR pin output setting
0: PLL lock error or transfer data parity error output (initial value)
1: DATAO data mute signal output
NPMODE
DATAO pin output setting when S/PDIF non-PCM data is received
0: Output (initial value)
1: Mute, "L" output
 When MPIO is no-load at an output setup, don't choose MPIO by DINSEL or THRSEL register.
 DATAO is muted when non-PCM data is detected at "NPMODE=1". But, due to it is not a data error, ERR output
PLL lock state ("L" output).
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