LC89091JA Datasheet, PDF (11/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
 The PLL clock output frequencies are shown below.
 When "PLLACC=1" and "PRSEL[1:0]=01" (512fs) are set, 128kHz, 176.4kHz and 192kHz S/PDIF reception results
in a PLL output frequency that exceeds 50MHz, so direct output to MCKO is not guaranteed.
Table 8.2: PLL Clock Output Frequencies (Bold settings are initial values.)
PLL clock output frequencies (MHz)
S/PDIF
fs
(kHz)
"PLLACC=0"
(Fixed multiple outputs for each input fs band)
"PLLDIV=00"
"PLLDIV=01"
"PLLDIV=10"
"PLLDIV=11"
"PLLACC=1"
(Fixed multiple outputs of input fs)
"PRSEL=00"
"PRSEL=01"
"PRSEL=10"
(256fs)
(512fs)
(128fs)
32
16.38
8.19
16.38
8.19
8.19
16.38
4.09
44.1
22.57
11.28
22.57
11.28
11.28
22.57
5.64
48
24.57
12.28
24.57
12.28
12.28
24.57
6.14
64
16.38
16.38
32.76
32.76
16.38
32.76
8.19
88.2
22.57
22.57
45.15
45.15
22.57
45.15
11.28
96
24.57
24.57
49.15
49.15
24.57
49.15
12.28
128
16.38
16.38
16.38
16.38
32.76
65.54 *
16.38
176.4
22.57
22.57
22.57
22.57
45.15
90.32 *
22.57
192
24.57
24.57
24.57
24.57
49.15
98.30 *
24.57
*: Direct output to the MCKO pin is not guaranteed.
8.5.3 XIN Source Master Clock (XIN, XOUT)
 Supply XIN with clocks all the time to be used in the following applications.
1) Clock source when the PLL is unlocked
2) PLL lock-in support
3) Calculation of the S/PDIF input data sampling frequency
 24.576MHz clock always has to supply to XIN.
 Normally, the oscillation amplifier automatically stops while the PLL is locked, but operation that always operates
regardless of the PLL status can also be set. This is set with the AMPOPR register.
The AMPOPR register must be set before S/PDIF input, or the setting must be completed while the PLL is unlocked.
 For fixing a system clock to a XIN clock, PLL is changed into an unlocking state. The ADMODE register always sets
PLL as an unlocking state.
 The output clock frequency at the time of XIN source is set up with the XOUTCK register.
Output Pin Name
Master clock
MCKO
Bit clock
BCKO
L/R clock
LRCKO
Table 8.3: List of Output Clock Frequencies
When PLL is unlocked,
XIN source clock (XIN input clock)
When PLL is locked,
PLL source clock (Internal VCO clock)
24.576 MHz
24.576 MHz
512fs
512fs
256fs
128fs
6.144 MHz
3.072 MHz
64fs
96 kHz
fs
48 kHz
No.A2172-11/30