LC89091JA Datasheet, PDF (12/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
8.5.4 Output clock switching (MCKO, BCKO, LRCKO)
 _{The clock source of PLL clock or XIN clock is switched automatically according to the PLL locked or unlocked status.}
 _{The output clock switches 2.7ms after the change of PLL status.}
PLL status
UNLOCK
LOCK

ERRWT register
ERR
MCKO
BCKO
LRCKO
2.7ms

XIN clock
PLL clock

(a) : Lock-in stage
PLL status
LOCK
UNLOCK

ERR
MCKO
BCKO
LRCKO
2.7ms

PLL clock
XIN clock

(b) : Unlock stage
Figure 8.5: Timing Chart of Output Clock Switching
8.5.5 Calculation of digital input data sampling frequency
 The input data sampling frequency is calculated using the XIN clock.
 In the "AMPOPR=0" mode (initial value) where the oscillation amplifier automatically stops according to the lock
status of the PLL, the input data sampling frequency is calculated during the ERR error period and completed when
the oscillation amplifier stops with holding the value. Therefore, the value remains unchanged until the PLL becomes
unlocked.
 If the oscillation amplifier is in a continuous operation mode ("AMPOPR=1"), calculation is repeated constantly.
Even if sampling changes within the PLL capture range for input data whose channel status sampling information
does not change, the calculation results that follow the input data can be read.
 The calculation results can be readout with the microcontroller interface.
No.A2172-12/30