LC89091JA Datasheet, PDF (15/30 Pages) ON Semiconductor – Digital Audio Interface Receiver

LC89091JA
8.6.5 Output data switching (SDIN, DATAO)
 _{DATAO outputs demodulation data when the PLL is locked, and outputs SDIN input data when the PLL is unlocked.}
This output is automatically switched according to the PLL locked/unlocked status.
 _{When SDIN input data is selected, SDIN input data must synchronize with clock source.}
 _{DATAO output switches via a mute period.}
 _{It adjusts by ERRWT register during the mute period at the time of PLL lock-in process.}
 _{It adjusts by DATWT register during the mute period at the time of PLL unlock process}
 _{With the DATMUT setting, the DATAO output data can be also muted forcibly.}
 _{NPMODE register can be muted the DATAO output data, when non-PCM data is received.}
Non-PCM data applies to the state of the channel status bit 1.
PLL status
ERR
ERR
DATAO
UNLOCK
ERRSEL=0
ERRSEL=1
SDIN data
LOCK
~~
ERRWT register
~~
Muted
(a) : Lock-in stage
~~
Demodulation data ~~
PLL status
ERR
ERR
DATAO
LOCK
UNLOCK
~~
DATWT register
ERRSEL=0
~~
ERRSEL=1
Demodulation data
Muted
(b) : Unlock stage
~~
SDIN data
~~
Figure 8.9: Timing Chart of DATAO Output Data Switching
No.A2172-15/30